US4996660A
Expired / Lapsed
US
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Selection of divisor multipliers in a floating point divide circuit
Assignee: International Business Machines Corp
•
Filing: 1989-04-17
•
Granted: 1991-02-26
•
Expires: 2009-04-17
Abstract
Abstract A multiple selector logic circuit for selecting divisor multiples in 2-bit, non-restoring divide sequences, which provides a proper and accurate quotient result and remainder, and which produces rounding and indication of exact or inexact result in conformance with ANSI/IEEE Standard 754-1985; the multiple selector logic circuit incorporates semiconductor circuits including a multiplier table having a particular matrix of multipliers which meet the standard.
Inventors
- 👤 Thomas J. Beacom
- 👤 Donald L. Freerksen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 06:52
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/535; G06F2207/00; G06F2207/535; G06F2207/5352; G06F7/483; G06F7/487; G06F7/4873; G06F7/499; G06F7/49942; G06F7/49947; G06F7/49957
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
96 words
In a floating point divide circuit of the type using a 2-bit, non-restoring division method, the improvement comprising a multiplier selection circuit having means for selecting a divisor multiple as a function of the most significant bits of the divisor and dividend, said multiplier selection circuit further comprising a semiconductor circuit having a selectable matrix of signals representative of possible divisor multipliers, none of said divisor multipliers being equal to three-fourths the value of the dividend divided by the divisor for all values of dividend and divisor within the range of most significant bits of interest.
Claim 2
Dependent Claim
96 words
In a floating point divide circuit of the type using a 2-bit, non-restoring division method, the improvement comprising a multiplier selection circuit having means for selecting a divisor multiple as a function of the most significant bits of the divisor and dividend, said multiplier selection circuit further comprising a semiconductor circuit having a selectable matrix of signals representative of possible divisor multipliers, none of said divisor multipliers being equal to three-fourths the value of the dividend divided by the divisor for all values of dividend and divisor within the range of most significant bits of interest.
Claim 3
Independent Claim
113 words
An apparatus for producing divisor multiples in a floating point arithmetic circuit, comprising a semiconductor circuit having a matrix of signal-producing cells therein, each of said cells being connected to sense the most significant bits of dividend registers and divisor registers, and each of said cells having means for producing a signal representative of a divisor multiplier in response to signals representative of the most significant bits of dividends and divisors, said signals representative of divisor multipliers further comprising signals representing divisor multipliers not equal to 3/4 D/V, where D and V respectively are all dividend and divisor values within the range of most significant bits to which said input selection circuit responds.
Claim 4
Independent Claim
113 words
An apparatus for producing divisor multiples in a floating point arithmetic circuit, comprising a semiconductor circuit having a matrix of signal-producing cells therein, each of said cells being connected to sense the most significant bits of dividend registers and divisor registers, and each of said cells having means for producing a signal representative of a divisor multiplier in response to signals representative of the most significant bits of dividends and divisors, said signals representative of divisor multipliers further comprising signals representing divisor multipliers not equal to 3/4 D/V, where D and V respectively are all dividend and divisor values within the range of most significant bits to which said input selection circuit responds.
Claim 5
Dependent Claim
19 words
The apparatus of claim 2, wherein said divisor multipliers further comprise the values 0, 1/2, 3/4, 1 and 3/2.
Claim 6
Independent Claim
186 words
An apparatus for producing divisor multiples in a floating point arthmetic circuit, comprising a semiconductor circuit having a matrix of signal-producing cells therein, each of said cells connected to an input selection circuit and having means for producing a signal representative of a divisor multiple to said input selection circuit, said matrix of signal-producing cells being responsive to signals representative of most significant bits of dividends and divisors; said matrix of signal-producing cells being constructed to produce specific divisor multiples according to the following combinations of divisors and dividends: __________________________________________________________________________
TRUE DIVISOR COMPLEMENT
DIVISOR
DIVIDEND
100
101
110
111
DIVIDEND 100
101
110
111
__________________________________________________________________________
000 0 0 0 0 000 3/2
3/2
1 1
001 0 0 0 0 001 3/2
1 1 1
010 1/2
1/2
1/2
1/2
010 1 1 1 3/4
011 1/2
1/2
1/2
1/2
011 1 1 3/4
3/4
100 1 1 3/4
3/4
100 1/2
1/2
1/2
1/2
101 1 1 3/4
3/4
101 1/2
1/2
1/2
1/2
110 3/2
1 1 1 110 0 0 0 0
111 3/2
3/2
1 1 111 0 0 0 0
__________________________________________________________________________
Claim 7
Independent Claim
186 words
An apparatus for producing divisor multiples in a floating point arthmetic circuit, comprising a semiconductor circuit having a matrix of signal-producing cells therein, each of said cells connected to an input selection circuit and having means for producing a signal representative of a divisor multiple to said input selection circuit, said matrix of signal-producing cells being responsive to signals representative of most significant bits of dividends and divisors; said matrix of signal-producing cells being constructed to produce specific divisor multiples according to the following combinations of divisors and dividends: __________________________________________________________________________
TRUE DIVISOR COMPLEMENT
DIVISOR
DIVIDEND
100
101
110
111
DIVIDEND 100
101
110
111
__________________________________________________________________________
000 0 0 0 0 000 3/2
3/2
1 1
001 0 0 0 0 001 3/2
1 1 1
010 1/2
1/2
1/2
1/2
010 1 1 1 3/4
011 1/2
1/2
1/2
1/2
011 1 1 3/4
3/4
100 1 1 3/4
3/4
100 1/2
1/2
1/2
1/2
101 1 1 3/4
3/4
101 1/2
1/2
1/2
1/2
110 3/2
1 1 1 110 0 0 0 0
111 3/2
3/2
1 1 111 0 0 0 0
__________________________________________________________________________
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-25 | 1994-08-27 | 1995-02-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-25 | 1998-08-27 | 1999-02-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-25 | 2002-08-27 | 2003-02-26 | $7700.00 | Window Closed / Lapsed |