Method and circuit for computing reciprocals

Claim 2

A circuit for generating an output signal representing an output number approximating a reciprocal of an input number of magnitude D represented by an input signal, said input signal comprising a set of M most significant bits and a set of N next most significant bits, the circuit comprising: first means responsive to said input signal for generating a first signal representing a first number approximating 1/A, wherein A is a number in accordance with said M most significant bits of said input signal; second means responsive to said input signal for generating a second signal representing a second number approximating B/A 2 , wherein B is a number approximately equal to D-A; and third means for combining said first and second signals to generate said output signal representing said output number.

Claim 3

The circuit in accordance with claim 1 wherein said second means comprises: means responsive to said input signal for generating a third signal representing a third number approximating 1/A 2 ; means responsive to said input signal for generating a fourth signal representing a fourth number equal to B; and multiplying means responsive to said third and fourth signals for generating said second signal representing said second number.

Claim 4

The circuit in accordance with claim 1 wherein said third means comprises means for subtracting said second number from said first number such that said output number is equal to a difference between said first and second numbers.

Claim 5

A circuit for generating an output signal representing an output floating point number approximately equal to an inverse of an input floating point number represented by an input signal, said input signal comprising an exponent bit set, a most significant mantissa bit set, and a less significant mantissa bit set, the circuit comprising: first means responsive to said input signal for generating a first signal representing a mantissa of a first floating point number approximately equal to a difference between a given number and an inverse of a second floating point number, said second floating point number being of magnitude defined by said exponent bit set and said most significant mantissa bit set of said input signal; second means responsive to said input signal for generating a second signal representing a mantissa of third floating point number substantially equal to a difference between said given number and a product of a square of an inverse of said second floating point number and a fourth floating point number defined by the exponent bit set and said less significant mantissa bit set of said input signal; third means responsive to said exponent bit set for generating a third signal representing exponents of said first and third floating point numbers; and fourth means responsive to said first, second and third signals for generating said output signal representing said output floating point number, said output floating point number being substantially equal to an arithmetic combination of said first and third floating point numbers.

Claim 6

A circuit for generating an output signal representing an output floating point number approximately equal to an inverse of an input floating point number represented by an input signal, said input signal comprising an exponent bit set, a most significant mantissa bit set, and a less significant mantissa bit set, the circuit comprising: first means responsive to said input signal for generating a first signal representing a mantissa of a first floating point number approximately equal to a difference between a given number and an inverse of a second floating point number, said second floating point number being of magnitude defined by said exponent bit set and said most significant mantissa bit set of said input signal; second means responsive to said input signal for generating a second signal representing a mantissa of third floating point number substantially equal to a difference between said given number and a product of a square of an inverse of said second floating point number and a fourth floating point number defined by the exponent bit set and said less significant mantissa bit set of said input signal; third means responsive to said exponent bit set for generating a third signal representing exponents of said first and third floating point numbers; and fourth means responsive to said first, second and third signals for generating said output signal representing said output floating point number, said output floating point number being substantially equal to an arithmetic combination of said first and third floating point numbers.

Claim 7

The circuit in accordance with claim 4 wherein said second and third means select said given number in accordance with said input floating point number such that said first and third floating point numbers have exponents equal to an exponent of a floating point number the magnitude of which is one half of an inverse of said input floating point number.

Claim 8

A circuit for generating an output signal representing an output floating point number approximating a reciprocal of an input floating point number of magnitude D represented by an input signal, said input signal comprising bits representing an exponent and a mantissa of said input floating point number, bits representing said mantissa including a set of M most significant bits and a set of N next most significant bits, where M and N are integers, the circuit comprising: first means responsive to said input signal for generating a first signal representing a first floating point number approximating (1/A)-C, wherein A is a magnitude of a floating point number represented by said input signal bits representing said exponent and said M most significant bits of said mantissa, and wherein C is a number of magnitude approximately equal to 1/2A; second means responsive to said input signal for generating a second signal representing a second floating point number approximating C-B/A 2 , wherein B is a floating point number approximately equal to D-A; and means for combining said first and second signals to generate said output signal representing said output floating point number.

Claim 9

A circuit for generating an output signal representing an output floating point number approximating a reciprocal of an input floating point number of magnitude D represented by an input signal, said input signal comprising bits representing an exponent and a mantissa of said input floating point number, bits representing said mantissa including a set of M most significant bits and a set of N next most significant bits, where M and N are integers, the circuit comprising: first means responsive to said input signal for generating a first signal representing a first floating point number approximating (1/A)-C, wherein A is a magnitude of a floating point number represented by said input signal bits representing said exponent and said M most significant bits of said mantissa, and wherein C is a number of magnitude approximately equal to 1/2A; second means responsive to said input signal for generating a second signal representing a second floating point number approximating C-B/A 2 , wherein B is a floating point number approximately equal to D-A; and means for combining said first and second signals to generate said output signal representing said output floating point number.

Claim 10

The circuit in accordance with claim 6 wherein C is of magnitude such that said first and second floating point numbers have exponents equal to an exponent of a floating point number of magnitude 1/2A.

Claim 13

The method in accordance with claim 8 wherein said step of generating said second signal comprises the substeps of: generating in response to said input signal a third signal representing a third number approximating 1/A 2 ; generating in response to said input signal a fourth signal representing a fourth number equal to B; and generating said second signal in response to said third and fourth signals, said second number represented by said second signal comprising a product of said third and fourth numbers represented by said third and fourth signals.

Claim 14

The method in accordance with claim 8 wherein said output number represents a difference between said first and second numbers.

Claim 17

The method in accordance with claim 11 wherein the magnitude of the number C is such that for each value of A said first and third floating point numbers have exponents equal to an exponent of a floating point number of magnitude 1/2A.