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US5770878A Expired / Lapsed US ⏱️ 0.0 years remaining

Trench MOS gate device

Assignee: Semiconductor Components Industries LLC
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Filing: 1996-04-10
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Granted: 1998-06-23
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Expires: 2016-04-10
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Abstract

Abstract The present invention is directed to an improved trench MOS gate device that comprises a trench whose floor and sidewalls include layers of dielectric material, the layers each having a controlled thickness dimension. These thickness dimensions are related by a controlled floor to sidewall layer thickness ratio, which is established by individually controlling the thickness of each of the floor and sidewall dielectric layers. This floor to sidewall layer thickness ratio is preferably at least 1 to 1, more preferably at least 1.2 to 1. Further in accordance with the present invention, a process for forming an improved trench MOS gate device comprises etching a trench in a silicon device wafer and forming layers of dielectric material on the trench floor and on the sidewalls, each layer having a controlled thickness dimension. The thickness dimensions are related by a controlled floor to sidewall layer thickness ratio that is preferably at least 1 to 1. When silicon dioxide is employed as the dielectric material, the layers preferably comprise a composite of thermally grown and deposited silicon dioxide. The trench containing the dielectric layers is filled with polysilicon, and an insulator layer is formed over the polysilicon, thereby forming a trench gate. A patterned electrically conducting metallic interconnect is formed over the trench gate.

Inventors

  • 👤 James Douglas Beasom

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 09:01
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/668; H10D30/01; H10D30/021; H10D30/028; H10D30/0291; H10D30/0297; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; H10D64/01342; H10D64/01344; H10D64/01346; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D64/693; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516

Claims Analysis

Total Claims: 17
Claim 1
Independent Claim 134 words
An improved trench MOS gate device comprising: a trench gate having a floor and sidewalls, said floor and said sidewalls comprising a layer of a dielectric material, said floor layer and said sidewall layers each having a substantially uniform controlled thickness dimension, wherein said substantially uniform thickness dimensions are related by a controlled floor to sidewall layer thickness ratio, said ratio being established by individually controlling the substantially uniform thickness of each of said floor and sidewall layers, and said thickness of said floor is greater than said thickness of said sidewall layers, wherein said floor layer and said sidewall layers each comprise a composite of thermally oxidized dielectric material having an oxygen concentration that decreases in a direction toward the floor or sidewall and deposited dielectric material having a substantially constant oxygen concentration.
Claim 2
Dependent Claim 134 words
An improved trench MOS gate device comprising: a trench gate having a floor and sidewalls, said floor and said sidewalls comprising a layer of a dielectric material, said floor layer and said sidewall layers each having a substantially uniform controlled thickness dimension, wherein said substantially uniform thickness dimensions are related by a controlled floor to sidewall layer thickness ratio, said ratio being established by individually controlling the substantially uniform thickness of each of said floor and sidewall layers, and said thickness of said floor is greater than said thickness of said sidewall layers, wherein said floor layer and said sidewall layers each comprise a composite of thermally oxidized dielectric material having an oxygen concentration that decreases in a direction toward the floor or sidewall and deposited dielectric material having a substantially constant oxygen concentration.
Claim 3
Dependent Claim 16 words
A trench MOS gate device according to claim 1, wherein said dielectric material comprises silicon dioxide.
Claim 4
Dependent Claim 19 words
A trench MOS gate device according to claim 1, wherein said thickness ratio is at least 1.2 to 1.
Claim 5
Dependent Claim 24 words
A trench MOS gate device according to claim 2, wherein said floor layer comprises silicon dioxide with a thickness of 300 to 3,000 angstroms.
Claim 6
Dependent Claim 24 words
A trench MOS gate device according to claim 2, wherein said sidewall layers comprise silicon dioxide with a thickness of 200 to 1,500 angstroms.
Claim 7
Dependent Claim 21 words
A trench MOS gate device according to claim 1, wherein said trench gate further comprises doped polysilicon disposed within said trench.
Claim 8
Dependent Claim 17 words
A trench MOS gate device according to claim 1, wherein said trench has an open-cell, stripe topology.
Claim 9
Dependent Claim 17 words
A trench MOS gate device according to claim 1, wherein said trench has a closed-cell, cellular topology.
Claim 10
Dependent Claim 17 words
A trench MOS gate device according to claim 8, wherein said trench has a square cellular topology.
Claim 11
Dependent Claim 17 words
A trench MOS gate device according to claim 8, wherein said trench has a hexagonal cellular topology.
Claim 12
Dependent Claim 12 words
A semiconductor device comprising the trench MOS gate device of claim 1.
Claim 13
Dependent Claim 10 words
A semiconductor device of claim 11 comprising a DMOS transistor.
Claim 14
Dependent Claim 12 words
A semiconductor device of claim 11 comprising an insulated gate bipolar transistor.
Claim 15
Dependent Claim 10 words
A semiconductor device of claim 11 comprising an MOS-controlled thyristor.
Claim 16
Dependent Claim 26 words
A trench MOS gate device according to claim 2, wherein said thermally grown silicon dioxide comprises a product of reaction of silicon in an oxygen-containing atmosphere.
Claim 17
Dependent Claim 26 words
A trench MOS gate device according to claim 2, wherein said deposited silicon dioxide comprises a chemical vapor deposited reaction product of a volatile silicon-containing compound.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-06-22 2001-12-22 2002-06-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-06-22 2005-12-22 2006-06-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-06-22 2009-12-22 2010-06-23 $7700.00 Window Closed / Lapsed

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