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Patent US5770517A successfully refreshed from Google Patents.
US5770517A
Expired / Lapsed
US
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Semiconductor fabrication employing copper plug formation within a contact area
Assignee: GlobalFoundries Inc
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Filing: 1997-03-21
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Granted: 1998-06-23
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Expires: 2017-03-21
Abstract
Abstract An integrated circuit fabrication process is provided in which copper is used as the contact plug material for a via. The via is a hole etched through an interlevel dielectric which is disposed upon a semiconductor topography, e.g., a silicon-based substrate having junctions therein. An inert implant may form an implant region within the semiconductor topography lying underneath the via. The process for forming the copper plug involves depositing a diffusion barrier upon the interlevel dielectric and within the via. Copper is then deposited via chemical vapor deposition upon the diffusion barrier such that the copper fills the entire via and forms a layer above the via. The copper is etched from all areas except from within the via, thereby forming a copper plug in the via. The resulting surface is then subjected to chemical-mechanical polishing before the diffusion barrier is removed from areas exclusive of the via. A conductive layer can be placed upon the interlevel dielectric and the copper plug to form a contact between the conductive layer and the semiconductor topography.
Inventors
- 👤 Mark I. Gardner
- 👤 Fred N. Hause
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 13:14
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/01; H10W20/031; H10W20/41; H10W20/425; Y; Y10; Y10S; Y10S257/00; Y10S257/915
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
76 words
A method for forming an integrated circuit, comprising: providing an interlevel dielectric disposed upon a semiconductor topography; removing a portion of the interlevel dielectric to form a via extending to a contact region of the semiconductor topography; implanting inert species through the via at an energy and concentration density sufficient to at least partially amorphize the contact region; depositing copper within the via and upon the interlevel dielectric; and removing said copper exclusive of said via.
Claim 2
Independent Claim
76 words
A method for forming an integrated circuit, comprising: providing an interlevel dielectric disposed upon a semiconductor topography; removing a portion of the interlevel dielectric to form a via extending to a contact region of the semiconductor topography; implanting inert species through the via at an energy and concentration density sufficient to at least partially amorphize the contact region; depositing copper within the via and upon the interlevel dielectric; and removing said copper exclusive of said via.
Claim 3
Dependent Claim
14 words
The method as recited in claim 1, wherein said interlevel dielectric comprises an oxide.
Claim 4
Dependent Claim
20 words
The method as recited in claim 1, wherein said via extends entirely through said interlevel dielectric to said semiconductor topography.
Claim 5
Dependent Claim
16 words
The method as recited in claim 1, wherein said semiconductor topography comprises a doped silicon-based substrate.
Claim 6
Dependent Claim
19 words
The method as recited in claim 1, wherein said semiconductor topography comprises a conductor patterned upon a dielectric material.
Claim 7
Dependent Claim
16 words
The method as recited in claim 1, wherein said removing said copper comprises chemical mechanical polishing.
Claim 8
Dependent Claim
17 words
The method as recited in claim 1, further comprising forming a conductor upon the remaining said copper.
Claim 9
Dependent Claim
18 words
The method as recited in claim 1, wherein said inert species comprises atomic silicon, germanium, argon or nitrogen.
Claim 10
Dependent Claim
12 words
The method as recited in claim 1, wherein said copper comprises silicon.
Claim 11
Independent Claim
83 words
A method for forming a contact structure of an integrated circuit, comprising: providing an interlayer dielectric disposed upon a topological surface, the interlevel dielectric having a via extending through the interlevel dielectric perpendicular to the topological surface; amorphizing the topological surface exposed by said via; depositing a diffusion barrier upon said amorphized topological surface and said interlevel dielectric; depositing copper upon said diffusion barrier; and removing said copper in areas exclusive of said via, thereby forming a copper plug bounded within said via.
Claim 12
Independent Claim
83 words
A method for forming a contact structure of an integrated circuit, comprising: providing an interlayer dielectric disposed upon a topological surface, the interlevel dielectric having a via extending through the interlevel dielectric perpendicular to the topological surface; amorphizing the topological surface exposed by said via; depositing a diffusion barrier upon said amorphized topological surface and said interlevel dielectric; depositing copper upon said diffusion barrier; and removing said copper in areas exclusive of said via, thereby forming a copper plug bounded within said via.
Claim 13
Dependent Claim
14 words
The method as recited in claim 9, wherein said interlevel dielectric comprises an oxide.
Claim 14
Dependent Claim
15 words
The method as recited in claim 9, wherein said via extends to said topological surface.
Claim 15
Dependent Claim
25 words
The method as recited in claim 9, wherein said topological surface comprises a surface of single crystalline silicon or a surface of a conductive layer.
Claim 16
Dependent Claim
16 words
The method as recited in claim 9, wherein said removing said copper comprises polishing or etching.
Claim 17
Dependent Claim
31 words
The method as recited in claim 9, wherein said amorphizing comprises implanting inert ions into said topological surface such that a majority of pre-existing atoms are displaced from the initial position.
Claim 18
Dependent Claim
15 words
The method as recited in claim 14, wherein said majority comprises greater than 50 percent.
References Cited (Backward Citations)
US4910169A
Cited
US4931410A
Cited
JPS6482620A
Cited
US5102826A
Cited
US5478780A
Cited
US5391517A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-22 | 2001-12-22 | 2002-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-22 | 2005-12-22 | 2006-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-22 | 2009-12-22 | 2010-06-23 | $7700.00 | Window Closed / Lapsed |