US5768548A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bus bridge for responding to received first write command by storing data and for responding to received second write command by transferring the stored data
Assignee: Intel Corp
•
Filing: 1997-01-15
•
Granted: 1998-06-16
•
Expires: 2017-01-15
Abstract
Abstract A bus with bus commands which optimize the management of buffers within a bus bridge is disclosed. The bus incorporates at least two types of write commands, a Postable Memory Write command and a Memory Write command. The Postable Memory Write command serves as a write command which additionally instructs the bus bridge that the processor will not be informed that the data transfer is complete, and thus, data may be posted in the bus bridge. In contrast, the Memory Write command serves as a write command which additionally instructs the bus bridge that the processor may be informed that the data transfer is complete, and that data should not, accordingly, be posted. These two write commands are used in combination such that a data transfer of a contiguous block of data utilizes Postable Memory Write commands until the final transaction in the transfer, at which time, a Memory Write command is used. The bus further incorporates at least two types of read commands, including a Memory Read Prefetch command and a Memory Read command. The Memory Read Pre-fetch command serves as a read command which additionally instructs the bus bridge to pre-fetch a first amount of data. The Memory Read command serves as a read command which additionally instructs the bridge to pre-fetch a second amount of data, or in an alternative usage, to read the data without pre-fetching.
Inventors
- 👤 Bruce Young
- 👤 Norman Rasmussen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:50
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/405; G06F13/4059
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
138 words
A computer system comprising: a memory; an agent sending a plurality of write commands, wherein each write command is one of a first type and a second type; and a bus bridge coupled to the agent and to the memory, the bus bridge being operative to respond to write commands based on type, the bus bridge responding to receiving a first write command of the first type from the agent by storing a first data element of the first write command, and then the bus bridge responding to receiving a second write command of the second type from the agent by first transferring any data elements stored by the bus bridge in response to write commands of the first type to the memory and subsequently transferring a second data element of the second write command to the memory.
Claim 2
Dependent Claim
138 words
A computer system comprising: a memory; an agent sending a plurality of write commands, wherein each write command is one of a first type and a second type; and a bus bridge coupled to the agent and to the memory, the bus bridge being operative to respond to write commands based on type, the bus bridge responding to receiving a first write command of the first type from the agent by storing a first data element of the first write command, and then the bus bridge responding to receiving a second write command of the second type from the agent by first transferring any data elements stored by the bus bridge in response to write commands of the first type to the memory and subsequently transferring a second data element of the second write command to the memory.
Claim 3
Dependent Claim
26 words
The computer system of claim 1 wherein the bus bridge sends an acknowledgment signal to the agent after transferring the second data element to the memory.
Claim 4
Dependent Claim
167 words
A computer system comprising: a memory; an agent sending a plurality of write commands, wherein each write command is one of a first type and a second type; a bus bridge coupled to the agent and to the memory, the bus bridge being operative to respond to write commands based on type, the bus bridge responding to receiving a first write command of the first type by storing a first data element of the first write command, the bus bridge responding to receiving a second write command of the second type by first transferring any data elements stored by the bus bridge in response to write commands of the first type to the memory and subsequently transferring a second data element of the second write command to the memory, wherein the bus bridge sends an acknowledgment signal to the agent after transferring the second data element to the memory; and a processor, the processor determining completion of data transfer by examining a predetermined location in the memory.
Claim 5
Dependent Claim
167 words
A computer system comprising: a memory; an agent sending a plurality of write commands, wherein each write command is one of a first type and a second type; a bus bridge coupled to the agent and to the memory, the bus bridge being operative to respond to write commands based on type, the bus bridge responding to receiving a first write command of the first type by storing a first data element of the first write command, the bus bridge responding to receiving a second write command of the second type by first transferring any data elements stored by the bus bridge in response to write commands of the first type to the memory and subsequently transferring a second data element of the second write command to the memory, wherein the bus bridge sends an acknowledgment signal to the agent after transferring the second data element to the memory; and a processor, the processor determining completion of data transfer by examining a predetermined location in the memory.
Claim 6
Dependent Claim
39 words
The computer system of claim 3 wherein the second write command stores the second data element in the predetermined location, the second data element having a value indicative of completion of data transfer from the agent to the memory.
Claim 7
Independent Claim
162 words
A method of writing data from an agent to a device with an address space, said method comprising the steps of: the agent sending a plurality of write commands to a bus bridge, each of the commands being one of a first type of write command and a second type of write command that is used as the last write command in a transfer of data elements, wherein the first type of write command indicates that any data element specified by the first type of write command is to be stored by the bus bridge, and wherein the second type of write command indicates that any data elements stored by the bus bridge in response to receiving write commands of the first type from the agent are to be transferred to the device first and that any data element specified by the second write command is to be subsequently transferred; and the bus bridge responding to each write command based on type.
Claim 8
Independent Claim
162 words
A method of writing data from an agent to a device with an address space, said method comprising the steps of: the agent sending a plurality of write commands to a bus bridge, each of the commands being one of a first type of write command and a second type of write command that is used as the last write command in a transfer of data elements, wherein the first type of write command indicates that any data element specified by the first type of write command is to be stored by the bus bridge, and wherein the second type of write command indicates that any data elements stored by the bus bridge in response to receiving write commands of the first type from the agent are to be transferred to the device first and that any data element specified by the second write command is to be subsequently transferred; and the bus bridge responding to each write command based on type.
Claim 9
Dependent Claim
33 words
The method of claim 5 further comprising the step of the bus bridge sending an acknowledgment signal to the agent to indicate completion of a data transfer from the agent to the device.
Claim 10
Independent Claim
151 words
A method of writing data from an agent to a device with an address space, said method comprising the steps of: the agent sending a plurality of write commands to a bus bridge, each of the commands being one of a first type of write command and a second type of write command, wherein the first type of write command indicates that any data element specified by the first type of write command indicates that any data elements stored by the bus bridge in response to receiving write commands of the first type from the agent are to be transferred to the device first and that any data element specified by the second write command is to be subsequently transferred; the bus bridge responding to each write command based on type; and determining completion of a data transfer from the agent to the device by examining a location in a memory.
Claim 11
Independent Claim
151 words
A method of writing data from an agent to a device with an address space, said method comprising the steps of: the agent sending a plurality of write commands to a bus bridge, each of the commands being one of a first type of write command and a second type of write command, wherein the first type of write command indicates that any data element specified by the first type of write command indicates that any data elements stored by the bus bridge in response to receiving write commands of the first type from the agent are to be transferred to the device first and that any data element specified by the second write command is to be subsequently transferred; the bus bridge responding to each write command based on type; and determining completion of a data transfer from the agent to the device by examining a location in a memory.
Claim 12
Dependent Claim
50 words
The method of claim 7 further comprising the step of the memory receiving the second data element in the memory, the memory writing the second data element in the location wherein the second data element comprises a value indicative of completion of data transfer from the agent to the device.
Claim 13
Dependent Claim
185 words
A computer system comprising: a first bus; a processor coupled to the first bus; a memory coupled to the first bus; a second bus; an agent coupled to the second bus, the agent being operative to send a first type of write command and a second type of write command, wherein the first and second types of write commands each include data to be written to the memory, wherein the second type of write command is used as the last write command in a transfer of data; and a bus bridge coupled the first bus and the second bus and coupled to receive write commands from the agent, the bus bridge being operative to respond to the first type of write command by storing data included in the first type of write command, the bus bridge being operative to respond to the second type of write command by first transferring any data stored by the bus bridge in response to the first type of write command to the memory and by subsequently transferring data specified by the second type of write command to the memory.
Claim 14
Dependent Claim
185 words
A computer system comprising: a first bus; a processor coupled to the first bus; a memory coupled to the first bus; a second bus; an agent coupled to the second bus, the agent being operative to send a first type of write command and a second type of write command, wherein the first and second types of write commands each include data to be written to the memory, wherein the second type of write command is used as the last write command in a transfer of data; and a bus bridge coupled the first bus and the second bus and coupled to receive write commands from the agent, the bus bridge being operative to respond to the first type of write command by storing data included in the first type of write command, the bus bridge being operative to respond to the second type of write command by first transferring any data stored by the bus bridge in response to the first type of write command to the memory and by subsequently transferring data specified by the second type of write command to the memory.
Claim 15
Dependent Claim
59 words
The computer system of claim 9, wherein the bus bridge is further operative to send an acknowledge signal to the agent in response to transferring data specified by the second type of write command to the memory, the agent being operative to inform the processor that data transfer to the memory is complete in response to the acknowledge signal.
Claim 16
Dependent Claim
205 words
A computer system comprising: a first bus; a processor coupled to the first bus; a memory coupled to the first bus; a second bus; an agent coupled to the second bus, the agent being operative to send a first type of write command and a second type of write command, wherein the first and second types of write commands each include data to be written to the memory: and a bus bridge coupled the first bus and the second bus and coupled to receive write commands from the agent, the bus bridge being operative to respond to the first type of write command by storing data included in the first type of write command, the bus bridge being operative to respond to the second type of write command by first transferring any data stored by the bus bridge in response to the first type of write command to the memory and by subsequently transferring data specified by the second type of write command to the memory, and wherein the second write command stores data having a value indicative of completion of data transfer in a predetermined location of the memory, the processor determining completion of data transfer by examining the predetermined location of the memory.
Claim 17
Dependent Claim
205 words
A computer system comprising: a first bus; a processor coupled to the first bus; a memory coupled to the first bus; a second bus; an agent coupled to the second bus, the agent being operative to send a first type of write command and a second type of write command, wherein the first and second types of write commands each include data to be written to the memory: and a bus bridge coupled the first bus and the second bus and coupled to receive write commands from the agent, the bus bridge being operative to respond to the first type of write command by storing data included in the first type of write command, the bus bridge being operative to respond to the second type of write command by first transferring any data stored by the bus bridge in response to the first type of write command to the memory and by subsequently transferring data specified by the second type of write command to the memory, and wherein the second write command stores data having a value indicative of completion of data transfer in a predetermined location of the memory, the processor determining completion of data transfer by examining the predetermined location of the memory.
Claim 18
Dependent Claim
190 words
A computer system comprising: a first bus; a processor coupled to the first bus; a memory coupled to the first bus; a second bus; an agent coupled to the second bus, the agent being operative to send a first type of read command and a second type of read command, the first and second types of read commands specifying an address of the memory from which data is to be read; and a bus bridge coupled the first bus and the second bus and coupled to receive read commands from the agent, the bus bridge being operative to respond to the first type of read command by fetching data from the address of the memory and from a first number of additional addresses of the memory and by storing the data in a data buffer, the bus bridge being operative to respond to the second type of read command by fetching data from the address of the memory and from a second number of additional addresses of the memory, wherein the first number of additional addresses is equal to at least one and exceeds the second number of additional addresses.
Claim 19
Dependent Claim
190 words
A computer system comprising: a first bus; a processor coupled to the first bus; a memory coupled to the first bus; a second bus; an agent coupled to the second bus, the agent being operative to send a first type of read command and a second type of read command, the first and second types of read commands specifying an address of the memory from which data is to be read; and a bus bridge coupled the first bus and the second bus and coupled to receive read commands from the agent, the bus bridge being operative to respond to the first type of read command by fetching data from the address of the memory and from a first number of additional addresses of the memory and by storing the data in a data buffer, the bus bridge being operative to respond to the second type of read command by fetching data from the address of the memory and from a second number of additional addresses of the memory, wherein the first number of additional addresses is equal to at least one and exceeds the second number of additional addresses.
Claim 20
Dependent Claim
17 words
The computer system of claim 12, wherein the second number of additional addresses is equal to zero.
Claim 21
Dependent Claim
15 words
The computer system of claim 12, wherein the second number of additional addresses exceeds zero.
Claim 22
Dependent Claim
130 words
A computer system, comprising: a first bus; a processor coupled to the first bus; a memory coupled to the first bus; a second bus; an agent coupled to the second bus, wherein the agent is capable of sending a first read command and a second read command that are each used to read data from the memory; and a bus bridge coupled to the first bus and the second bus, and also coupled to receive a plurality of read commands from the agent, the bus bridge responding to the first read command by reading a first memory address space and pre-fetching additional sequential data to the first memory address space, the bus bridge responding to the second read command by reading a second memory address space without pre-fetching any data.
Claim 23
Dependent Claim
130 words
A computer system, comprising: a first bus; a processor coupled to the first bus; a memory coupled to the first bus; a second bus; an agent coupled to the second bus, wherein the agent is capable of sending a first read command and a second read command that are each used to read data from the memory; and a bus bridge coupled to the first bus and the second bus, and also coupled to receive a plurality of read commands from the agent, the bus bridge responding to the first read command by reading a first memory address space and pre-fetching additional sequential data to the first memory address space, the bus bridge responding to the second read command by reading a second memory address space without pre-fetching any data.
Claim 24
Dependent Claim
150 words
A computer system, comprising: a first bus; a processor coupled to the first bus; a memory coupled to the first bus; a second bus; an agent coupled to the second bus, wherein the agent is capable of sending a first read command and a second read command that are each used to read data from the memory; and a bus bridge coupled to the first bus and the second bus, and also coupled to receive a plurality of read commands from the agent, the bus bridge responding to the first read command to read more than a full cache line from the memory by pre-fetching a predetermined number of additional cache lines, the bus bridge responding to the second read command to read less than a full cache line from the memory by pre-fetching one cache line of data, and wherein the computer system can support variable cache length pre-fetching.
Claim 25
Dependent Claim
150 words
A computer system, comprising: a first bus; a processor coupled to the first bus; a memory coupled to the first bus; a second bus; an agent coupled to the second bus, wherein the agent is capable of sending a first read command and a second read command that are each used to read data from the memory; and a bus bridge coupled to the first bus and the second bus, and also coupled to receive a plurality of read commands from the agent, the bus bridge responding to the first read command to read more than a full cache line from the memory by pre-fetching a predetermined number of additional cache lines, the bus bridge responding to the second read command to read less than a full cache line from the memory by pre-fetching one cache line of data, and wherein the computer system can support variable cache length pre-fetching.
Claim 26
Dependent Claim
20 words
The computer system of claim 16, wherein the predetermined number of addition cache lines is a number greater than one.
References Cited (Backward Citations)
US4148011A
Cited
US4347567A
Cited
US4467447A
Cited
US4410942A
Cited
US4587609A
Cited
US4763249A
Cited
US4716527A
Cited
US4719569A
Cited
US4807178A
Cited
US5167022A
Cited
US5274784A
Cited
US5117486A
Cited
US5185865A
Cited
US5224213A
Cited
US5269005A
Cited
US5430860A
Cited
US5333276A
Cited
US5265211A
Cited
US5434997A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-15 | 2001-12-15 | 2002-06-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-15 | 2005-12-15 | 2006-06-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-15 | 2009-12-15 | 2010-06-16 | $7700.00 | Window Closed / Lapsed |