Clock signal supplying circuit

Claim 2

A clock signal supplying circuit, comprising: a clock signal generating circuit for generating a clock signal; a first signal path in which a frequency-dividing circuit for dividing down said clock signal is provided; a second signal path having a signal-delay-quantity substantially equivalent to a signal-delay-quantity of the first path and permitting said clock signal to pass through undivided, said second signal path including a delay circuit having a structure substantially equivalent to the frequency dividing circuit; and a controlled circuit which receives a signal from the first signal path and a signal from the second signal path, and having an operation controlled by said signals from the first and second signal paths.

Claim 3

A clock signal supplying circuit, comprising: a clock signal generating circuit for generating a clock signal; a frequency-dividing circuit which receives said clock signal, and outputs a first signal with said clock signal divided down; a delay circuit having a signal-delay-quantity substantially equivalent to a signal-delay-quantity between input of the clock signal and output of the first signal said frequency-dividing circuit, outputting a second signal after receiving said clock signal, and having a, structure substantially equivalent to the frequency-dividing circuit; and a controlled circuit which receives the first signal outputted from said frequency-dividing circuit and the second signal outputted from said delay circuit, and having an operation controlled by the first and second signals.

Claim 4

A clock signal supplying circuit, comprising: a clock signal generating circuit for generating a clock signal; a frequency-dividing circuit which receives said clock signal, and outputs a first signal with said clock signal divided down; a delay circuit having a signal-delay-quantity substantially equivalent to a signal-delay-quantity between input of the clock signal and output of the first signal said frequency-dividing circuit, outputting a second signal after receiving said clock signal, and having a, structure substantially equivalent to the frequency-dividing circuit; and a controlled circuit which receives the first signal outputted from said frequency-dividing circuit and the second signal outputted from said delay circuit, and having an operation controlled by the first and second signals.

Claim 5

A clock signal supplying circuit according to claim 2, wherein said frequency-dividing circuit includes at least one D-type flip-flop circuit, and said delay circuit includes D-type flip-flop circuit of the same number as said frequency-dividing circuit.

Claim 6

A clock signal supplying circuit according to claim 2, further comprising: a selection circuit in which either the first signal outputted from said frequency-dividing circuit or the second signal outputted from said delay circuit is selected in accordance with a selection control signal, and the selected signal is supplied to said controlled circuit.

Claim 7

A clock signal supplying circuit according to claim 3, wherein each of said D-type flip-flop circuit provided at said frequency-dividing circuit includes a clock input terminal, a data input terminal, a data output terminal for providing said first signal, an inversion-data output terminal and a clear signal terminal for receiving a clear signal, said clock signal being inputted to said clock input terminal, said inversion-data output terminal being connected to said data input terminal, and each of said D-type flip-flop circuit provided at said delay circuit includes a clock input terminal, a data input terminal, a data output terminal for providing said second signal, an inversion-data output terminal, and a clear signal terminal, said clock signal being inputted both to said clock input terminal and said clear signal terminal, a logic signal of "H"-level being inputted to said data input terminal.

Claim 8

A clock signal supplying circuit comprising: a clock signal generating circuit for generating a clock signal; a first frequency-dividing circuit which receives said clock signal, and outputs a first signal with said clock signal divided down; a first delay circuit having signal-delay-quantity substantially equivalent to signal-delay-quantity between input signal and output signal of said first frequency-dividing circuit, and outputting a second signal after receiving said clock signal; a first selection circuit in which either the first signal outputted from said first frequency-dividing circuit or the second signal outputted from said first delay circuit is selected in accordance with a selection control signal, and the selected signal is outputted as a third signal; a second delay circuit having signal-delay-quantity substantially equivalent to signal-delay-quantity between said clock signal and the output of said first selection circuit, and outputting a fourth signal after receiving said clock signal; and a controlled circuit which receives both of the third signal outputted from said first selection circuit and the fourth signal outputted from said second delay circuit, an operation thereof being controlled by the third and the fourth signals.

Claim 9

A clock signal supplying circuit comprising: a clock signal generating circuit for generating a clock signal; a first frequency-dividing circuit which receives said clock signal, and outputs a first signal with said clock signal divided down; a first delay circuit having signal-delay-quantity substantially equivalent to signal-delay-quantity between input signal and output signal of said first frequency-dividing circuit, and outputting a second signal after receiving said clock signal; a first selection circuit in which either the first signal outputted from said first frequency-dividing circuit or the second signal outputted from said first delay circuit is selected in accordance with a selection control signal, and the selected signal is outputted as a third signal; a second delay circuit having signal-delay-quantity substantially equivalent to signal-delay-quantity between said clock signal and the output of said first selection circuit, and outputting a fourth signal after receiving said clock signal; and a controlled circuit which receives both of the third signal outputted from said first selection circuit and the fourth signal outputted from said second delay circuit, an operation thereof being controlled by the third and the fourth signals.

Claim 10

A clock signal supplying circuit according to claim 6, wherein said first frequency-dividing circuit includes at least one D-type flip-flop circuit, and said first delay circuit includes D-type flip-flop circuit of the same number as said first frequency-dividing circuit.

Claim 11

A clock signal supplying circuit according to claim 7, wherein each of said D-type flip-flop circuit provided at said first frequency-dividing circuit includes a clock input terminal, a data input terminal, a data output terminal for providing said first signal, an inversion-data output terminal and a clear signal terminal for receiving a clear signal, said clock signal being inputted to said clock input terminal, said inversion-data output terminal being connected to said data input terminal, and each of said D-type flip-flop circuit provided at said first delay circuit includes a clock input terminal, a data input terminal, a data output terminal for providing said second signal, an inversion-data output terminal, and a clear signal terminal, said clock signal being inputted both to said clock input terminal and said clear signal terminal, a logic signal of "H"-level being inputted to said data input terminal.

Claim 12

A clock signal supplying circuit according to claim 6, wherein said second delay circuit includes: a second frequency-dividing circuit which receives said clock signal, and which has signal-delay-quantity substantially equivalent to signal-delay-quantity between input signal and output signal of said first frequency-dividing circuit, and which outputs a fifth signal after dividing down said clock signal; a third delay circuit which has signal-delay-quantity substantially equivalent to signal-delay-quantity between input signal and output signal of said first frequency-dividing circuit, and which outputs a sixth signal after receiving said clock signal; and a second selection circuit which is formed equivalently to the first selection circuit, in which either the fifth signal outputted from said second frequency-dividing circuit or the sixth signal outputted from said third delay circuit is selected in accordance with a second selection control signal, and the selected signal is outputted as the fourth signal.

Claim 13

A clock signal supplying circuit according to claim 9, wherein the second selection control signal is fixed to a first logic level, and the second selection circuit regularly selects the fifth signal outputted from the second frequency-dividing circuit, outputting as the fourth signal.

Claim 14

A clock signal supplying circuit according to claim 9, wherein the second selection control signal is fixed to a second logic level, and the second selection circuit regularly selects the sixth signal outputted from the third delay circuit, outputting as the fourth signal.

Claim 15

A clock signal supplying circuit according to claim 9, wherein said second frequency-dividing circuit includes D-type flip-flop circuit of a same number as said first frequency-dividing circuit and said third delay circuit includes D-type flip-flop circuit of a same number as said second frequency-dividing circuit.

Claim 16

A clock signal supplying circuit according to claim 12, wherein each of said D-type flip-flop circuit provided at said second frequency-dividing circuit includes a clock input terminal, a data input terminal, a data output terminal for providing said fifth signal, an inversion-data output terminal and a clear signal terminal coupled to ground, said clock signal being inputted to said clock input terminal, said inversion-data output terminal being connected to said data input terminal, and each of said D-type flip-flop circuit provided at said third delay circuit includes a clock input terminal, a data input terminal, a data output terminal for providing said sixth signal, an inversion-data output terminal, and a clear signal terminal, said clock signal being inputted both to said clock input terminal and said clear-signal terminal, a logic signal of "H"-level being inputted to said data input terminal.

Claim 17

A clock signal supplying circuit, comprising: a clock signal generating circuit for generating a clock signal; a first signal-output circuit, said first signal-output circuit comprising a first frequency-dividing circuit, receiving said clock signal and outputting a first signal with said clock signal divided down, a first delay circuit having signal-delay-quantity substantially equivalent to signal-delay-quantity between input signal and output signal of said first frequency-dividing circuit, and, outputting a second signal after receiving said clock signal, and a first selection circuit in which either said first signal outputted from said first frequency-dividing circuit or said second signal outputted from said first delay circuit is selected in accordance with a first selection control signal, and the selected signal is outputted as a third signal; and at least one second signal-output circuit, said second signal-output circuit comprising a second frequency-dividing circuit which receives said clock signal, and which has a signal-delay-quantity substantially equivalent to the signal-delay-quantity between input signal and output signal of said first frequency-dividing circuit, and which outputs a fourth signal after dividing down said clock signal; a second delay circuit which has a signal-delay-quantity substantially equivalent to the signal-delay-quantity between input signal and output signal of said first frequency-dividing circuit, and which outputs a fifth signal after receiving said clock signal; and a second selection circuit, in which either said fourth signal outputted from said second frequency-dividing circuit or said fifth signal outputted from said second delay circuit is selected in accordance with a second selection control signal, and the selected signal is outputted as a sixth signal.

Claim 18

A clock signal supplying circuit, comprising: a clock signal generating circuit for generating a clock signal; a first signal-output circuit, said first signal-output circuit comprising a first frequency-dividing circuit, receiving said clock signal and outputting a first signal with said clock signal divided down, a first delay circuit having signal-delay-quantity substantially equivalent to signal-delay-quantity between input signal and output signal of said first frequency-dividing circuit, and, outputting a second signal after receiving said clock signal, and a first selection circuit in which either said first signal outputted from said first frequency-dividing circuit or said second signal outputted from said first delay circuit is selected in accordance with a first selection control signal, and the selected signal is outputted as a third signal; and at least one second signal-output circuit, said second signal-output circuit comprising a second frequency-dividing circuit which receives said clock signal, and which has a signal-delay-quantity substantially equivalent to the signal-delay-quantity between input signal and output signal of said first frequency-dividing circuit, and which outputs a fourth signal after dividing down said clock signal; a second delay circuit which has a signal-delay-quantity substantially equivalent to the signal-delay-quantity between input signal and output signal of said first frequency-dividing circuit, and which outputs a fifth signal after receiving said clock signal; and a second selection circuit, in which either said fourth signal outputted from said second frequency-dividing circuit or said fifth signal outputted from said second delay circuit is selected in accordance with a second selection control signal, and the selected signal is outputted as a sixth signal.

Claim 19

A clock signal supplying circuit according to claim 14, wherein said first frequency-dividing circuit includes at least one D-type flip-flop circuit and said first delay circuit includes D-type flip-flop circuit of the same number as said first frequency-dividing circuit, said second frequency-dividing circuit includes D-type flip-flop circuit of the same number as said first frequency-dividing circuit, said second delay circuit includes D-type flip-flop circuit of the same number as said first divided frequency circuit.

Claim 20

A clock signal supplying circuit according to claim 15, wherein each of said D-type flip-flop circuit provided at said first and second frequency-dividing circuits includes a clock input terminal, a data input terminal, a data output terminal for providing one of said first and fourth signals, an inversion-data output terminal and a clear signal terminal for receiving a clear signal, said clock signal being inputted to said clock input terminal, said inversion-data output terminal being connected to said data input terminal, and each of said D-type flip-flop circuit provided at said first and second delay circuits includes a clock input terminal, a data input terminal, a data output terminal for providing one of said second and fifth signal, an inversion-data output terminal, and a clear signal terminal, said clock signal being inputted both to said clock input terminal and said clear signal terminal, a logic signal of "H"-level being inputted to said data input terminal.

Claim 21

A clock signal supplying circuit, comprising: a clock signal generating circuit for generating a clock signal; a frequency-dividing circuit having a first D-type flip-flop circuit including a clock input, terminal, a data input terminal, a data output terminal, an inversion-data output terminal, a cleat signal terminal, said clock signal is inputted to said clock input terminal, and both of said inversion-data output terminal and said data input terminal are connected thereto, outputting a first signal from said data output terminal; a delay circuit having a second D-type flip-flop circuit including a clock input terminal, a data input terminal, a first data output terminal, an inversion-data output terminal, a clear signal terminal, said clock signal is inputted both to said clock input terminal and said clear signal terminal outputting a second signal from said first data output terminal, and a logic signal of "H"-level is inputted to said data input terminal; and a controlled circuit which receives said first signal outputted from said frequency-dividing circuit and said second signal outputted from said delay circuit, an operation thereof being controlled by said first and said second signals.

Claim 22

A clock signal supplying circuit, comprising: a clock signal generating circuit for generating a clock signal; a frequency-dividing circuit having a first D-type flip-flop circuit including a clock input, terminal, a data input terminal, a data output terminal, an inversion-data output terminal, a cleat signal terminal, said clock signal is inputted to said clock input terminal, and both of said inversion-data output terminal and said data input terminal are connected thereto, outputting a first signal from said data output terminal; a delay circuit having a second D-type flip-flop circuit including a clock input terminal, a data input terminal, a first data output terminal, an inversion-data output terminal, a clear signal terminal, said clock signal is inputted both to said clock input terminal and said clear signal terminal outputting a second signal from said first data output terminal, and a logic signal of "H"-level is inputted to said data input terminal; and a controlled circuit which receives said first signal outputted from said frequency-dividing circuit and said second signal outputted from said delay circuit, an operation thereof being controlled by said first and said second signals.

Claim 23

A clock signal supplying circuit, comprising: a clock signal generating circuit for generating a clock signal; a frequency-dividing circuit which receives said clock signal and outputs a first signal with said clock signal divided down and includes at least one D-type flip-flop circuit, said D-type flip-flop circuit including a clock input terminal, a data input terminal, a data output terminal for providing said first signal, an inversion-data output terminal, and a clear signal terminal for receiving a clear signal, said clock signal being inputted to said clock input terminal and said inversion-data output terminal being connected to said data input terminal; a delay circuit having a structure substantially equivalent to the frequency-dividing circuit, including at least one D-type flip-flop circuit and having a signal-delay-quantity substantially equivalent to a signal-delay-quantity between input of the clock signal and output of the first signal said frequency-dividing circuit, said delay circuit outputting a second signal after receiving said clock signal, and said D-type flip-flop circuit including a clock input terminal, a data input terminal, a data output terminal for providing said second signal, an inversion-data output terminal, and a clear signal terminal, with said clock signal being inputted to said clock input terminal and said clear signal terminal, and a logic signal of "H"-level being inputted to said data input terminal; and a controlled circuit which receives the first signal outputted from said frequency-dividing circuit and the second signal outputted from said delay circuit, and having an operation controlled by the first and second signals.

Claim 24

A clock signal supplying circuit, comprising: a clock signal generating circuit for generating a clock signal; a frequency-dividing circuit which receives said clock signal and outputs a first signal with said clock signal divided down and includes at least one D-type flip-flop circuit, said D-type flip-flop circuit including a clock input terminal, a data input terminal, a data output terminal for providing said first signal, an inversion-data output terminal, and a clear signal terminal for receiving a clear signal, said clock signal being inputted to said clock input terminal and said inversion-data output terminal being connected to said data input terminal; a delay circuit having a structure substantially equivalent to the frequency-dividing circuit, including at least one D-type flip-flop circuit and having a signal-delay-quantity substantially equivalent to a signal-delay-quantity between input of the clock signal and output of the first signal said frequency-dividing circuit, said delay circuit outputting a second signal after receiving said clock signal, and said D-type flip-flop circuit including a clock input terminal, a data input terminal, a data output terminal for providing said second signal, an inversion-data output terminal, and a clear signal terminal, with said clock signal being inputted to said clock input terminal and said clear signal terminal, and a logic signal of "H"-level being inputted to said data input terminal; and a controlled circuit which receives the first signal outputted from said frequency-dividing circuit and the second signal outputted from said delay circuit, and having an operation controlled by the first and second signals.