Automated method and system for designing an optimized integrated circuit

Claim 2

An automated method for designing an integrated circuit, said method comprising: in response to receipt of a high-level functional description of an integrated circuit including both control logic and data flow logic, constructing an initial substrate layout of said integrated circuit, said initial substrate layout including a plurality of subcircuits electrically connected by a plurality of interconnects, wherein said initial substrate layout is constructed based upon estimated timing characteristics of said plurality of subcircuits; arranging particular ones of said plurality of subcircuits to optimize performance of said substrate layout of said integrated circuit, wherein said arrangement of particular ones of said plurality of subcircuits is performed independently for subcircuits implementing control logic and subcircuits implementing data flow logic; determining performance characteristics of said substrate layout, including timing characteristics of said plurality of subcircuits and resistive and capacitive characteristics of said plurality of interconnects; in response to a determination of said performance characteristics of said substrate layout, adjusting operating power levels of selected subcircuits among said plurality of subcircuits and resistances of selected ones of said plurality of interconnects to optimize performance of said substrate layout, wherein said adjustment of operating power levels of said selected subcircuits is performed independently for subcircuits implementing control logic and subcircuits implementing data flow logic; thereafter, repeating said step of determining performance characteristics of said substrate layout; and in response to said repeated determination of said performance characteristics of said substrate layout, finalizing routing of said plurality of interconnects electrically connecting said plurality of subcircuits, wherein performance of said substrate layout of said integrated circuit is optimized by iteratively refining said initial substrate layout utilizing performance characteristic data.

Claim 3

The automated method for designing an integrated circuit of claim 1, and further comprising: repeating said step of determining performance characteristics of said substrate layout; and in response to said repeated determination of said performance characteristics of said substrate layout, optimizing sizes of selected ones of said plurality of subcircuits utilizing as design constraints previously determined operating power levels and relative positions of said selected ones of said plurality of subcircuits and finalized routing of said plurality of interconnects.

Claim 4

The automated method for designing an integrated circuit of claim 1, and further comprising: determining if a performance characteristic of said initial substrate layout exceeds a predetermined benchmark; and in response to a failure of said performance characteristic of said initial substrate layout to exceed said predetermined benchmark, revising said high-level functional description.

Claim 5

The automated method for designing an integrated circuit of claim 1, wherein said integrated circuit is subject to a design constraint of a maximum substrate area, said method further comprising: subsequent to said step of adjusting operating power levels of selected subcircuits among said plurality of subcircuits, verifying that all of said plurality of subcircuits fit within said maximum substrate area without overlap.

Claim 6

The automated method for designing an integrated circuit of claim 1, wherein said step of finalizing routing of said plurality of interconnects further comprises tuning resistances of particular ones of said plurality of interconnects.

Claim 7

The automated method for designing an integrated circuit of claim 5, wherein said steps of adjusting resistances of selected ones of said plurality of interconnects and tuning resistances of said particular ones of said plurality of interconnects comprise adjusting widths of said selected ones and said particular ones of said plurality of interconnects.

Claim 8

The automated method for designing an integrated circuit of claim 1, and further comprising verifying performance of said final substrate layout of said integrated circuit.

Claim 9

The automated method for designing an integrated circuit of claim 1, and further comprising: choosing said selected subcircuits from among said plurality of subcircuits in response to a determination of said performance characteristic of said substrate layout, said performance characteristic of said substrate layout specifying an estimated performance for each of said plurality of subcircuits, wherein each of said selected subcircuits among said plurality of subcircuits exhibits a proportionally greater deviation from a maximum ideal performance than nonselected subcircuits among said plurality of subcircuits.

Claim 10

An automated system for designing an integrated circuit, said system comprising: means for constructing an initial substrate layout of an integrated circuit in response to receipt of a high-level functional description of said integrated circuit including both control logic and data flow logic, said initial substrate layout including a plurality of subcircuits electrically connected by a plurality of interconnects, wherein said initial substrate layout is constructed based upon estimated timing characteristics of said plurality of subcircuits; means for arranging particular ones of said plurality of subcircuits to optimize performance of said substrate layout of said integrated circuit, wherein said means for arranging particular ones of said plurality of subcircuits operates on subcircuits implementing control logic independently of subcircuits implementing data flow logic; means for determining performance characteristics of said substrate layout, including timing characteristics of said plurality of subcircuits and resistive and capacitive characteristics of said plurality of interconnects; means for adjusting operating power levels of selected subcircuits among said plurality of subcircuits and resistances of selected ones of said plurality of interconnects to optimize performance of said substrate layout in response to a determination of said performance characteristics of said substrate layout, wherein said means for adjusting operating power levels of selected subcircuits operates on subcircuits implementing control logic independently of subcircuits implementing data flow logic; means for thereafter repeating said determination of performance characteristics of said substrate layout; and means for finalizing routing of said plurality of interconnects electrically connecting said plurality of subcircuits in response to said repeated determination of said performance characteristics of said substrate layout, wherein performance of said substrate layout of said integrated circuit is optimized by iteratively refining said initial substrate layout utilizing performance characteristic data.

Claim 11

An automated system for designing an integrated circuit, said system comprising: means for constructing an initial substrate layout of an integrated circuit in response to receipt of a high-level functional description of said integrated circuit including both control logic and data flow logic, said initial substrate layout including a plurality of subcircuits electrically connected by a plurality of interconnects, wherein said initial substrate layout is constructed based upon estimated timing characteristics of said plurality of subcircuits; means for arranging particular ones of said plurality of subcircuits to optimize performance of said substrate layout of said integrated circuit, wherein said means for arranging particular ones of said plurality of subcircuits operates on subcircuits implementing control logic independently of subcircuits implementing data flow logic; means for determining performance characteristics of said substrate layout, including timing characteristics of said plurality of subcircuits and resistive and capacitive characteristics of said plurality of interconnects; means for adjusting operating power levels of selected subcircuits among said plurality of subcircuits and resistances of selected ones of said plurality of interconnects to optimize performance of said substrate layout in response to a determination of said performance characteristics of said substrate layout, wherein said means for adjusting operating power levels of selected subcircuits operates on subcircuits implementing control logic independently of subcircuits implementing data flow logic; means for thereafter repeating said determination of performance characteristics of said substrate layout; and means for finalizing routing of said plurality of interconnects electrically connecting said plurality of subcircuits in response to said repeated determination of said performance characteristics of said substrate layout, wherein performance of said substrate layout of said integrated circuit is optimized by iteratively refining said initial substrate layout utilizing performance characteristic data.

Claim 12

The automated system for designing an integrated circuit of claim 9, and further comprising: means for repeating said means for determining performance characteristics of said substrate layout; and means, responsive to said repeated determination of said performance characteristics of said substrate layout, for optimizing sizes of selected ones of said plurality of subcircuits utilizing as design constraints previously determined operating power levels and relative positions of said selected ones of said plurality of subcircuits and finalized routing of said plurality of interconnects.

Claim 13

The automated system for designing an integrated circuit of claim 9, and further comprising: means for determining if a performance characteristic of said initial substrate layout exceeds a predetermined benchmark; and means for revising said high-level functional description in response to a failure of said performance characteristic of said initial substrate layout to exceed said predetermined benchmark.

Claim 14

The automated system for designing an integrated circuit of claim 9, wherein said integrated circuit is subject to a design constraint of a maximum substrate area, said system further comprising: means for verifying that all of said plurality of subcircuits fit within said maximum substrate area without overlap subsequent to adjusting operating power levels of selected subcircuits among said plurality of subcircuits.

Claim 15

The automated system for designing an integrated circuit of claim 9, wherein said means for finalizing routing of said plurality of interconnects further comprises means for tuning resistances of particular ones of said plurality of interconnects.

Claim 16

The automated system for designing an integrated circuit of claim 13, wherein said means for adjusting resistances of selected ones of said plurality of interconnects and means for tuning resistances of said particular ones of said plurality of interconnects comprise means for adjusting widths of said selected ones and said particular ones of said plurality of interconnects.

Claim 17

The automated system for designing an integrated circuit of claim 9, and further comprising means for verifying performance of said final substrate layout of said integrated circuit.

Claim 18

The automated system for designing an integrated circuit of claim 9, and further comprising: means for choosing said selected subcircuits from among said plurality of subcircuits in response to a determination of said performance characteristic of said substrate layout, said performance characteristic of said substrate layout specifying an estimated performance for each of said plurality of subcircuits, wherein each of said selected subcircuits among said plurality of subcircuits exhibits a proportionally greater deviation from a maximum ideal performance than nonselected subcircuits among said plurality of subcircuits.

Claim 19

A computer program product stored on a computer readable media for causing a data processing system to design an integrated circuit, said computer program product comprising: instruction means for causing said data processing system to construct an initial substrate layout of an integrated circuit in response to receipt of a high-level functional description of said integrated circuit including both control logic and data flow logic, said initial substrate layout including a plurality of subcircuits electrically connected by a plurality of interconnects, wherein said initial substrate layout is constructed based upon estimated timing characteristics of said plurality of subcircuits; instruction means for causing said data processing system to arrange particular ones of said plurality of subcircuits to optimize performance of said substrate layout of said integrated circuit, wherein said instruction means for causing said data processing system to arrange particular ones of said plurality of subcircuits operates on subcircuits implementing control logic independently of subcircuits implementing data flow logic; instruction means for causing said data processing system to determine performance characteristics of said substrate layout, including timing characteristics of said plurality of subcircuits and resistive and capacitive characteristics of said plurality of interconnects; instruction means for causing said data processing system to adjust operating power levels of selected subcircuits among said plurality of subcircuits and resistances of selected ones of said plurality of interconnects to optimize performance of said substrate layout in response to a determination of said performance characteristics of said substrate layout, wherein said instruction means for causing said data processing system to adjust operating lower levels of selected subcircuits among said plurality of subcircuits operates on subcircuits implementing control logic independently of subcircuits implementing data flow logic; instruction means for causing said data processing system to thereafter repeat said determination of performance characteristics of said substrate layout; and instruction means for causing said data processing system to finalize routing of said plurality of interconnects electrically connecting said plurality of subcircuits in response to said repeated determination of said performance characteristics of said substrate layout, wherein performance of said substrate layout of said integrated circuit is optimized by iteratively refining said initial substrate layout utilizing performance characteristic data.

Claim 20

A computer program product stored on a computer readable media for causing a data processing system to design an integrated circuit, said computer program product comprising: instruction means for causing said data processing system to construct an initial substrate layout of an integrated circuit in response to receipt of a high-level functional description of said integrated circuit including both control logic and data flow logic, said initial substrate layout including a plurality of subcircuits electrically connected by a plurality of interconnects, wherein said initial substrate layout is constructed based upon estimated timing characteristics of said plurality of subcircuits; instruction means for causing said data processing system to arrange particular ones of said plurality of subcircuits to optimize performance of said substrate layout of said integrated circuit, wherein said instruction means for causing said data processing system to arrange particular ones of said plurality of subcircuits operates on subcircuits implementing control logic independently of subcircuits implementing data flow logic; instruction means for causing said data processing system to determine performance characteristics of said substrate layout, including timing characteristics of said plurality of subcircuits and resistive and capacitive characteristics of said plurality of interconnects; instruction means for causing said data processing system to adjust operating power levels of selected subcircuits among said plurality of subcircuits and resistances of selected ones of said plurality of interconnects to optimize performance of said substrate layout in response to a determination of said performance characteristics of said substrate layout, wherein said instruction means for causing said data processing system to adjust operating lower levels of selected subcircuits among said plurality of subcircuits operates on subcircuits implementing control logic independently of subcircuits implementing data flow logic; instruction means for causing said data processing system to thereafter repeat said determination of performance characteristics of said substrate layout; and instruction means for causing said data processing system to finalize routing of said plurality of interconnects electrically connecting said plurality of subcircuits in response to said repeated determination of said performance characteristics of said substrate layout, wherein performance of said substrate layout of said integrated circuit is optimized by iteratively refining said initial substrate layout utilizing performance characteristic data.

Claim 21

The computer program product of claim 17, and further comprising: instruction means for causing said data processing system to repeat said determination of performance characteristics of said substrate layout; and instruction means, responsive to said repeated determination of said performance characteristics of said substrate layout, for causing said data processing system to optimize sizes of selected ones of said plurality of subcircuits utilizing as design constraints previously determined operating power levels and relative positions of said selected ones of said plurality of subcircuits and finalized routing of said plurality of interconnects.

Claim 22

The computer program product of claim 17, and further comprising: instruction means for causing said data processing system to determine if a performance characteristic of said initial substrate layout exceeds a predetermined benchmark; and instruction means for causing said data processing system to revise said high-level functional description in response to a failure of said performance characteristic of said initial substrate layout to exceed said predetermined benchmark.

Claim 23

The computer program product of claim 17, wherein said integrated circuit is subject to a design constraint of a maximum substrate area, said computer program product further comprising: instruction means for causing said data processing system to verify that all of said plurality of subcircuits fit within said maximum substrate area without overlap subsequent to adjusting operating power levels of selected subcircuits among said plurality of subcircuits.

Claim 24

The computer program product of claim 17, wherein said instruction means for finalizing routing of said plurality of interconnects further comprises instruction means for causing said data processing system to tune resistances of particular ones of said plurality of interconnects.

Claim 25

The computer program product of claim 21, wherein said instruction means for adjusting resistances of selected ones of said plurality of interconnects and instruction means for tuning resistances of said particular ones of said plurality of interconnects comprise instruction means for causing said data processing system to adjust widths of said selected ones and said particular ones of said plurality of interconnects.

Claim 26

The computer program product of claim 17, and further comprising instruction means for causing said data processing system to verify performance of said final substrate layout of said integrated circuit.

Claim 27

The computer program product of claim 17, and further comprising: instruction means for causing said data processing system to choose said selected subcircuits from among said plurality of subcircuits in response to a determination of said performance characteristic of said substrate layout, said performance characteristic of said substrate layout specifying an estimated performance for each of said plurality of subcircuits, wherein each of said selected subcircuits among said plurality of subcircuits exhibits a proportionally greater deviation from a maximum ideal performance than nonselected subcircuits among said plurality of subcircuits.