Patent US5764070A successfully refreshed from Google Patents.
US5764070A
Expired / Lapsed
US
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Structure for testing bare integrated circuit devices
Assignee: Microchip Technology Caldicot Ltd
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Filing: 1996-02-21
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Granted: 1998-06-09
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Expires: 2016-02-21
Abstract
Abstract A test probe structure for making connections to a bare integrated circuit device or a wafer to be tested comprises a multilayer printed circuit probe arm which carries at its tip an MCM-D type substrate having a row of microbumps on its underside to make the required connections. The probe arm is supported at a shallow angle to the surface of the device or wafer, and the MCM-D type substrate is formed with the necessary passive components to interface with the device under test. Four such probe arms may be provided, one on each side of the device under test.
Inventors
- 👤 David John Pedder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:09
CPC Classifications
G; G01; G01R; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/06772; G01R31/00; G01R31/28; G01R31/2801; G01R31/2805
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
122 words
A structure for testing bare integrated circuit devices, comprising: device support means for supporting an integrated circuit device to be tested; a substrate having formed on one surface thereof a multilayer metal-polyimide dielectric interconnect structure; and a multilayer printed circuit board probe means for supporting said substrate at an angle with respect to said device such that an edge of said one surface of said substrate is adjacent said device, said substrate being secured to an end of said printed circuit board probe means by a thermoplastic adhesive, said multilayer interconnect structure having a plurality of contact pads formed along said edge of said substrate and a like plurality of microbump contacts formed on respective ones of said plurality of contact pads.
Claim 2
Dependent Claim
122 words
A structure for testing bare integrated circuit devices, comprising: device support means for supporting an integrated circuit device to be tested; a substrate having formed on one surface thereof a multilayer metal-polyimide dielectric interconnect structure; and a multilayer printed circuit board probe means for supporting said substrate at an angle with respect to said device such that an edge of said one surface of said substrate is adjacent said device, said substrate being secured to an end of said printed circuit board probe means by a thermoplastic adhesive, said multilayer interconnect structure having a plurality of contact pads formed along said edge of said substrate and a like plurality of microbump contacts formed on respective ones of said plurality of contact pads.
Claim 3
Dependent Claim
14 words
A structure in accordance with claim 1 wherein the substrate comprises a sapphire wafer.
Claim 4
Dependent Claim
14 words
A structure in accordance with claim 1 wherein the substrate comprises a silicon wafer.
Claim 5
Dependent Claim
20 words
A structure in accordance with claim 1 wherein the multi-layer metal-polymer dielectric substrate incorporates a plurality of passive circuit components.
Claim 6
Dependent Claim
31 words
A structure in accordance with claim 1 wherein electrical connections between the substrate and conductors on the printed circuit board probe means are made by way of short wire bond links.
Claim 7
Dependent Claim
24 words
A structure in accordance with claim 5 wherein said conductors on the printed circuit board probe means provide power supply, ground and signal lines.
Claim 8
Dependent Claim
32 words
A structure in accordance with claim 1 including at least one discrete circuit component mounted on said printed circuit board probe means adjacent said substrate and electrically connected to said interconnect structure.
Claim 9
Dependent Claim
38 words
A structure in accordance with claim 1 wherein there are provided a plurality of said printed circuit board probe means each having a respective substrate secured thereto to make contact to said integrated circuit device to be tested.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-08 | 2001-12-08 | 2002-06-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-08 | 2005-12-08 | 2006-06-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-08 | 2009-12-08 | 2010-06-09 | $7700.00 | Window Closed / Lapsed |