US5761517A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System and method for reducing power consumption in high frequency clocked circuits
Assignee: International Business Machines Corp
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Filing: 1996-08-14
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Granted: 1998-06-02
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Expires: 2016-08-14
Abstract
Abstract A system and method are provided which automatically change the output of an oscillator clock prior to its input to dynamic logic circuit elements as a system clock signal. The oscillator clock signal is controlled based upon a signal generated by a sensor which determines the power consumption of the integrated circuit. The frequency of the clocked signal is reduced (or increased) incrementally based upon the output of the sensor which detects the level of a specific circuit characteristic, relating to electrical power consumption. A pattern generator is used to input a digital signal to a series of interconnected registers which make up a loadable shift register. The output of the pattern generator is based upon the input from the sensor. The bits shifted through the shift register are ANDed with the oscillator clock signal to control the frequency of the system clock.
Inventors
- 👤 Christopher McCall Durham
- 👤 Peter Juergen Klim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:56
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/324; G06F1/04; G06F1/08; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
49 words
A circuit, comprising: means for providing an oscillator clock signal at a first frequency; means for determining a power consumption state of said circuit; and means for generating a system clock signal by incrementally deleting pulses in synchronism with the oscillator clock signal based upon said power consumption state.
Claim 2
Dependent Claim
49 words
A circuit, comprising: means for providing an oscillator clock signal at a first frequency; means for determining a power consumption state of said circuit; and means for generating a system clock signal by incrementally deleting pulses in synchronism with the oscillator clock signal based upon said power consumption state.
Claim 3
Dependent Claim
32 words
A circuit according to claim 1 wherein said means for determining a power consumption state comprises means for outputting a power control signal based upon said power consumption state of said circuit.
Claim 4
Dependent Claim
27 words
A circuit according to claim 2 further comprising means for providing a clock control signal to said means for generating in accordance with said power control signal.
Claim 5
Dependent Claim
36 words
A circuit according to claim 3 wherein said means for generating further comprises a plurality of sequentially connected stages which output control data to a next said sequential stage in response to said clock control signal.
Claim 6
Dependent Claim
33 words
A circuit according to claim 4 wherein said means for generating further comprises means for comparing said control data with said oscillator clock signal to set the frequency of said system clock signal.
Claim 7
Dependent Claim
57 words
A circuit according to claim 5 wherein said means for generating further comprises: means for determining, over a predetermined period of time, whether said power control signal has changed state; and means for altering said clock control signal to cause the frequency of said system clock signal to be reduced when said power control signal remains active.
Claim 8
Dependent Claim
57 words
A circuit according to claim 5 wherein said means for generating further comprises: means for determining, over a predetermined period of time, whether said power control signal has changed state; and means for altering said clock control signal to cause the frequency of said system clock signal to be reduced when said power control signal remains inactive.
Claim 9
Independent Claim
64 words
A method for regulating the frequency of a system clock signal in accordance with power consumption of an electrical circuit, comprising the steps of: providing an oscillator clock signal at a first frequency; determining a power consumption state of said circuit; and generating a system clock signal by incrementally deleting pulses in synchronism with the oscillator clock signal based upon said power consumption state.
Claim 10
Independent Claim
64 words
A method for regulating the frequency of a system clock signal in accordance with power consumption of an electrical circuit, comprising the steps of: providing an oscillator clock signal at a first frequency; determining a power consumption state of said circuit; and generating a system clock signal by incrementally deleting pulses in synchronism with the oscillator clock signal based upon said power consumption state.
Claim 11
Dependent Claim
33 words
A method according to claim 8 wherein said step of determining a power consumption state comprises the step of outputting a power control signal based upon said power consumption state of said circuit.
Claim 12
Dependent Claim
23 words
A method according to claim 9 further comprising the step of providing a clock control signal in accordance with said power control signal.
Claim 13
Dependent Claim
40 words
A method according to claim 10 wherein said step of generating further comprises the step of outputting, in response to said clock control signal, control data from a first register in a plural bit shift register to a next register.
Claim 14
Dependent Claim
34 words
A method according to claim 11 wherein said step of generating further comprises the step of comparing said control data with said oscillator clock signal to determine the frequency of said system clock signal.
Claim 15
Dependent Claim
56 words
A method according to claim 12 wherein said step of generating further comprises the steps of: determining, over a predetermined period of time, whether said power control signal has changed state; and altering said clock control signal to cause the frequency of said system clock signal to be reduced when said power control signal remains active.
Claim 16
Dependent Claim
56 words
A method according to claim 12 wherein said step of generating further comprises the steps of: determining, over a predetermined period of time, whether said power control signal has changed state; and altering said clock control signal to cause the frequency of said system clock signal to be increased when said power control signal remains inactive.
References Cited (Backward Citations)
US4093871A
Cited
US4716551A
Cited
US5086387A
Cited
US5222239A
Cited
US5073838A
Cited
US5465367A
Cited
US5664201A
Cited
US5628001A
Cited
JPH06175956A
Cited
US5511203A
Cited
US5630148A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-01 | 2001-12-01 | 2002-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-01 | 2005-12-01 | 2006-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-01 | 2009-12-01 | 2010-06-02 | $7700.00 | Window Closed / Lapsed |