US5761516A
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Single chip multiprocessor architecture with internal task switching synchronization bus
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1996-05-03
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Granted: 1998-06-02
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Expires: 2016-05-03
Abstract
Abstract A plurality of processors which can be the same or different are formed on a single integrated circuit chip together with a memory controller and an I/O controller, and are interconnected by a data transfer bus. The processors can have larger word lengths and operate at higher speeds than comparable single chip processors due to reduced latency and signal path lengths. The processors are further interconnected by a processor synchronization bus which enables one processor to cause another processor to perform a task by generating an interrupt and passing the required parameters. The parameters can be passed via shared memory, or via a bidirectional data section of the processor synchronization bus. A processor running a large scale CAD or similar application can cause a smaller processor to perform I/O tasks in native code. A multiprocessor system can be configured as including a Single-Chip module (SCM), a Multi-Chip Module (MCM), Board-Level Product (BPL), or as a box-level product which includes a power supply.
Inventors
- 👤 Michael D. Rostoker
- 👤 Douglas B. Boyle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 17:54
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
99 words
A single-chip multiprocessor system, comprising: a first processor; a second processor; and a processor synchronization bus which interconnects said first and second processors; said first processor being adapted, in response to a task more advantageously performed by said second processor, to enable said second processor to perform said task more advantageously performed by said second processor via said processor synchronization bus; said second processor being adapted, in response to a task more advantageously performed by said first processor, to enable said first processor to perform said task more advantageously performed by said first processor via said processor synchronization bus.
Claim 2
Dependent Claim
99 words
A single-chip multiprocessor system, comprising: a first processor; a second processor; and a processor synchronization bus which interconnects said first and second processors; said first processor being adapted, in response to a task more advantageously performed by said second processor, to enable said second processor to perform said task more advantageously performed by said second processor via said processor synchronization bus; said second processor being adapted, in response to a task more advantageously performed by said first processor, to enable said first processor to perform said task more advantageously performed by said first processor via said processor synchronization bus.
Claim 3
Dependent Claim
42 words
A system as in claim 1, in which the processor synchronization bus comprises: a first interrupt line which enables the first processor to interrupt the second processor; and a second interrupt line which enables the second processor to interrupt the first processor.
Claim 4
Dependent Claim
87 words
A system as in claim 2, in which: the first processor causes the second processor to perform a task by causing an interrupt to be applied to the second processor over the first interrupt line, and passing parameters required for performing the task to the second processor; and the second processor causes the first processor to perform a task by causing an interrupt to be applied to the first processor over the second interrupt line, and passing parameters required for performing the task to the first processor.
Claim 5
Dependent Claim
69 words
A system as in claim 3, further comprising: a memory controller; and a data transfer bus to which the first and second processors and the memory controller are connected to a memory; in which the first processor passes said parameters to the second processor using the memory controller and the memory; and the second processor passes said parameters to the first processor using the memory controller and the memory.
Claim 6
Dependent Claim
49 words
A system as in claim 3, in which: the processor synchronization bus further comprises a bidirectional data section; the first processor passes said parameters to the second processor using the bidirectional data section; and the second processor passes said parameters to the first processor using the bidirectional data section.
Claim 7
Dependent Claim
16 words
A system as in claim 1, in which the first and second processors are substantially identical.
Claim 8
Dependent Claim
15 words
A system as in claim 1, in which the first and second processors are different.
Claim 9
Dependent Claim
18 words
A system as in claim 1, in which the first and second processors use a same instruction set.
Claim 10
Dependent Claim
17 words
A system as in claim 1, in which the first and second processors use different instruction sets.
Claim 11
Dependent Claim
17 words
A system as in claim 9, in which said different instruction sets have different numbers of bits.
Claim 12
Dependent Claim
124 words
A single-chip multiprocessor system, comprising: a first processor; a second processor; a processor synchronization bus which interconnects said first and second processors; a memory controller; an I/O controller; and a data bus to which said first and second processors, said memory controller and said I/O controller are connected; said first processor being adapted, in response to a task more advantageously performed by said second processor, to enable said second processor to perform said task more advantageously performed by said second processor via said processor synchronization bus; said second processor being adapted, in response to a task more advantageously performed by said first processor, to enable said first processor to perform said task more advantageously performed by said first processor via said processor synchronization bus.
Claim 13
Dependent Claim
124 words
A single-chip multiprocessor system, comprising: a first processor; a second processor; a processor synchronization bus which interconnects said first and second processors; a memory controller; an I/O controller; and a data bus to which said first and second processors, said memory controller and said I/O controller are connected; said first processor being adapted, in response to a task more advantageously performed by said second processor, to enable said second processor to perform said task more advantageously performed by said second processor via said processor synchronization bus; said second processor being adapted, in response to a task more advantageously performed by said first processor, to enable said first processor to perform said task more advantageously performed by said first processor via said processor synchronization bus.
Claim 14
Dependent Claim
42 words
A system as in claim 11, in which the processor synchronization bus comprises: a first interrupt line which enables the first processor to interrupt the second processor; and a second interrupt line which enables the second processor to interrupt the first processor.
Claim 15
Dependent Claim
87 words
A system as in claim 12, in which: the first processor causes the second processor to perform a task by causing an interrupt to be applied to the second processor over the first interrupt line, and passing parameters required for performing the task to the second processor; and the second processor causes the first processor to perform a task by causing an interrupt to be applied to the first processor over the second interrupt line, and passing parameters required for performing the task to the first processor.
Claim 16
Dependent Claim
37 words
A system as in claim 13, in which: the first processor passes said parameters to the second processor using the memory controller; and the second processor passes said parameters to the first processor using the memory controller.
Claim 17
Dependent Claim
48 words
A system as in claim 13, in which: the processor synchronization bus comprises a bidirectional data section; the first processor passes said parameters to the second processor using the bidirectional data section; and the second processor passes said parameters to the first processor using the bidirectional data section.
Claim 18
Dependent Claim
16 words
A system as in claim 11, in which the first and second processors are substantially identical.
Claim 19
Dependent Claim
15 words
A system as in claim 11, in which the first and second processors are different.
Claim 20
Dependent Claim
18 words
A system as in claim 11, in which the first and second processors use a same instruction set.
Claim 21
Dependent Claim
17 words
A system as in claim 11, in which the first and second processors use different instruction sets.
Claim 22
Dependent Claim
17 words
A system as in claim 19, in which said different instruction sets have different numbers of bits.
Claim 23
Dependent Claim
25 words
A system as in claim 11, in which the first and second processors, memory controller and I/O controller are configured as a Single-Chip Module (SCM).
Claim 24
Dependent Claim
25 words
A system as in claim 11, in which the first and second processors, memory controller and I/O controller are configured as a Multi-Chip Module (MCM).
Claim 25
Dependent Claim
25 words
A system as in claim 11, in which the first and second processors, memory controller and I/O controller are configured as a Board-Level Product (BLP).
Claim 26
Dependent Claim
24 words
A system as in claim 11, in which the first and second processors, memory controller and I/O controller are configured as a box-level product.
Claim 27
Independent Claim
167 words
A method of processing data using a multiprocessor system, in which: the multiprocessor system comprises; a first processor; a second processor; and a processor synchronization bus which interconnects said first and second processors and includes a first interrupt line and a second interrupt line said first processor being adapted, in response to a task more advantageously performed by said second processor, to enable said second processor to perform said task more advantageously performed by said second processor via said processor synchronization bus; said second processor being adapted, in response to a task more advantageously performed by said first processor, to enable said first processor to perform said task more advantageously performed by said first processor via said processor synchronization bus; and the method comprises controlling the first processor to cause the second processor to perform a task, including the steps of: (a) applying an interrupt to the second processor over the first interrupt line, and (b) passing parameters required for performing the task to the second processor.
Claim 28
Independent Claim
167 words
A method of processing data using a multiprocessor system, in which: the multiprocessor system comprises; a first processor; a second processor; and a processor synchronization bus which interconnects said first and second processors and includes a first interrupt line and a second interrupt line said first processor being adapted, in response to a task more advantageously performed by said second processor, to enable said second processor to perform said task more advantageously performed by said second processor via said processor synchronization bus; said second processor being adapted, in response to a task more advantageously performed by said first processor, to enable said first processor to perform said task more advantageously performed by said first processor via said processor synchronization bus; and the method comprises controlling the first processor to cause the second processor to perform a task, including the steps of: (a) applying an interrupt to the second processor over the first interrupt line, and (b) passing parameters required for performing the task to the second processor.
Claim 29
Dependent Claim
55 words
A method as in claim 25, in which the method further comprises controlling the second processor to cause the first processor to perform a task, including the steps of: (c) applying an interrupt to the first processor over the second interrupt line, and (d) passing parameters required for performing the task to the first processor.
Claim 30
Dependent Claim
47 words
A method as in claim 25, in which: the multiprocessor system further comprises: a memory; and a data transfer bus to which the first and second processors and the memory are connected; in which step (b) comprises passing said parameters to the second processor using the memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-01 | 2001-12-01 | 2002-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-01 | 2005-12-01 | 2006-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-01 | 2009-12-01 | 2010-06-02 | $7700.00 | Window Closed / Lapsed |