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US5760599A
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Method and apparatus for testing semiconductor integrated circuits
Assignee: Sharp Corp
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Filing: 1996-08-06
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Granted: 1998-06-02
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Expires: 2016-08-06
Abstract
Abstract A current detecting resistance is inserted somewhere in a path for feeding a power source current to a supply voltage terminal VDD of a DUT from a power source of a testing apparatus, and from the potential difference at both ends, a pulse form change due to the state transition of a CMOS circuit in the DUT contained in the power source current is detected. The number of pulse form changes is counted by a counter. In the DUT, a test pattern is applied from a driver, an expected value preset according to the test pattern and the count of the counter are compared, and it is judged whether or not the DUT is in good quality. The current due to a pulse form transition to be detected by the current detecting resistance is larger than the current flowing when the CMOS circuit in the DUT is in a static state, and therefore, the resistance value of the current detecting resistance may be set smaller, so that the time required for testing may be shortened.
Inventors
- 👤 Masayuki Ehiro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:53
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/30; G01R31/3004; G01R29/00; G01R29/02; G01R31/26; G01R31/319; G01R31/31917; G01R31/31924; H; H10; H10P; H10P74/00
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
87 words
A method of testing a semiconductor integrated circuit for defects, the method comprising the steps of: supplying a power source current to the semiconductor integrated circuit; applying a test signal pattern to the semiconductor integrated circuit; counting pulses contained in the supplied power source current of the semiconductor integrated circuit, which pulses exceed a predetermined reference current level, while applying the test signal pattern to the semiconductor integrated circuit; and comparing the count with a predetermined expected value to determine whether the semiconductor integrated circuit is defective.
Claim 2
Independent Claim
87 words
A method of testing a semiconductor integrated circuit for defects, the method comprising the steps of: supplying a power source current to the semiconductor integrated circuit; applying a test signal pattern to the semiconductor integrated circuit; counting pulses contained in the supplied power source current of the semiconductor integrated circuit, which pulses exceed a predetermined reference current level, while applying the test signal pattern to the semiconductor integrated circuit; and comparing the count with a predetermined expected value to determine whether the semiconductor integrated circuit is defective.
Claim 3
Dependent Claim
49 words
The method according to claim 1, wherein the applied test signal pattern includes a plurality of predetermined patterns, and every time the state changes after application of each pattern, the count is sequentially in real time compared with an expected value calculated preliminarily according to the test signal pattern.
Claim 4
Dependent Claim
33 words
The method according to claim 1, wherein after application of the test signal pattern, the final count of the pulses is compared with an expected value calculated preliminarily according to the test pattern.
Claim 5
Dependent Claim
61 words
The method according to claim 2, wherein the counting step is performed using a resistance for detecting the power source current in a power source current supply path, whereby the potential difference across the resistance is compared to a reference voltage and converted to a voltage pulse when the reference voltage is exceeded, the voltage pulse being fed into a counter.
Claim 6
Dependent Claim
61 words
The method according to claim 3, wherein the counting step is performed using a resistance for detecting the power source current in a power source current supply path, whereby the potential difference across the resistance is compared to a reference voltage and converted to a voltage pulse when the reference voltage is exceeded, the voltage pulse being fed into a counter.
Claim 7
Dependent Claim
102 words
A testing apparatus for determining whether a semiconductor integrated circuit is defective, the apparatus comprising: pattern generating means for generating a test pattern and feeding said test pattern into an input of the semiconductor integrated circuit; detecting means for detecting a power source current of the semiconductor integrated circuit and producing a pulse when the power source current exceeds a predetermined current level; counting means for counting said pulses produced by said detecting means; and comparing means for comparing the count obtained by said counting means with an expected count value based upon said test pattern generated by said pattern generating means.
Claim 8
Dependent Claim
102 words
A testing apparatus for determining whether a semiconductor integrated circuit is defective, the apparatus comprising: pattern generating means for generating a test pattern and feeding said test pattern into an input of the semiconductor integrated circuit; detecting means for detecting a power source current of the semiconductor integrated circuit and producing a pulse when the power source current exceeds a predetermined current level; counting means for counting said pulses produced by said detecting means; and comparing means for comparing the count obtained by said counting means with an expected count value based upon said test pattern generated by said pattern generating means.
Claim 9
Dependent Claim
47 words
The testing apparatus according to claim 6, wherein said detecting means includes a resistance external to the semiconductor integrated circuit being tested, said resistance being in a power source current path, said detecting means detecting the power source current by detecting the potential difference across said resistance.
Claim 10
Dependent Claim
82 words
The testing apparatus according to claim 7, wherein said test pattern includes a plurality of predetermined patterns, and said counting means includes a latch circuit which is reset when each pattern of said test pattern is generated and which is set when a signal sent out for said detecting means exceeds a predetermined reference level, as well as a counter for counting a number of times of the state transition between the reset state and the set state of said latch circuit.
Claim 11
Dependent Claim
22 words
The testing apparatus according to claim 6, wherein the semiconductor integrated circuit is part of said apparatus and is a CMOS inverter.
Claim 12
Dependent Claim
16 words
The method according to claim 4, wherein the resistance is external to the semiconductor integrated circuit.
Claim 13
Dependent Claim
16 words
The method according to claim 5, wherein the resistance is external to the semiconductor integrated circuit.
Claim 14
Dependent Claim
15 words
The method according to claim 1, wherein the comparing step uses a three-bit binary counter.
Claim 15
Dependent Claim
26 words
The method according to claim 1, wherein the tested semiconductor integrated circuit is indicated as defective when the count is greater than the predetermined expected value.
Claim 16
Dependent Claim
16 words
The method according to claim 1, wherein the tested semiconductor integrated circuit is a CMOS device.
Claim 17
Independent Claim
79 words
A method for monitoring the operation of a semiconductor integrated circuit, comprising the steps of: (a) supplying power source current to a power input terminal of the semiconductor integrated circuit; (b) detecting a number of times that the power source current supplied in said step (a) exceeds a predetermined current level; and (c) comparing the number detected in said step (b) against a predetermined number, a result of said comparing indicating whether the semiconductor integrated circuit is operating defectively.
Claim 18
Independent Claim
79 words
A method for monitoring the operation of a semiconductor integrated circuit, comprising the steps of: (a) supplying power source current to a power input terminal of the semiconductor integrated circuit; (b) detecting a number of times that the power source current supplied in said step (a) exceeds a predetermined current level; and (c) comparing the number detected in said step (b) against a predetermined number, a result of said comparing indicating whether the semiconductor integrated circuit is operating defectively.
Claim 19
Dependent Claim
31 words
The method according to claim 15, wherein said step (a) is performed concurrently with the step of: (d) supplying a signal pattern to an input terminal of the semiconductor integrated circuit.
Claim 20
Dependent Claim
43 words
The method according to claim 16, wherein the signal pattern of said step (d) is a test signal pattern for testing whether the semiconductor integrated circuit is defective, and the predetermined number in said step (c) is based upon the test signal pattern.
Claim 21
Dependent Claim
62 words
The method according to claim 15, wherein said step (b) includes the substeps of: (b-1) detecting a voltage across a resistance external to the semiconductor integrated circuit, the voltage being generated by the power source current; and (b-2) producing a pulse when the detected voltage exceeds a predetermined voltage level; and (b-3) counting the number of pulses produced in said substep (b-2).
Claim 22
Dependent Claim
35 words
The method according to claim 18, wherein the resistance is connected in series with the power input terminal of the semiconductor integrated circuit such that all of the power source current passes through the resistance.
Claim 23
Dependent Claim
45 words
The method according to claim 15, wherein the semiconductor integrated circuit is a CMOS inverter including a P-channel transistor having a source, and the power input terminal is connected to the source of the P-channel transistor, the power input terminal for receiving a positive voltage.
Claim 24
Independent Claim
105 words
An apparatus for monitoring the operation of a semiconductor integrated circuit having a power input terminal for receiving power source current, said apparatus comprising: a current to voltage converter for detecting a current supplied to the power input terminal of the semiconductor integrated circuit and for producing a voltage pulse when the detected current exceeds a predetermined current level; a counter for counting the number of pulses produced by said current to voltage converter; and a comparitor for comparing the number of pulses counted by the counter against a predetermined number, an output of said comparitor indicating whether the semiconductor integrated circuit is operating defectively.
Claim 25
Independent Claim
105 words
An apparatus for monitoring the operation of a semiconductor integrated circuit having a power input terminal for receiving power source current, said apparatus comprising: a current to voltage converter for detecting a current supplied to the power input terminal of the semiconductor integrated circuit and for producing a voltage pulse when the detected current exceeds a predetermined current level; a counter for counting the number of pulses produced by said current to voltage converter; and a comparitor for comparing the number of pulses counted by the counter against a predetermined number, an output of said comparitor indicating whether the semiconductor integrated circuit is operating defectively.
Claim 26
Dependent Claim
52 words
The apparatus according to claim 21, wherein the semiconductor integrated circuit has a signal input terminal, and said apparatus further comprises a signal pattern generator for supplying a signal pattern to the signal input terminal of the semiconductor integrated circuit concurrently with the supply of the current to the power input terminal.
Claim 27
Dependent Claim
45 words
The apparatus according to claim 22, wherein the signal pattern supplied by said signal pattern generator is a test signal pattern for testing whether the semiconductor integrated circuit is defective, and the predetermined number used by said comparitor is based upon said test signal pattern.
Claim 28
Dependent Claim
61 words
The apparatus according to claim 21, wherein said current to voltage converter includes: a resistance element, a voltage being generated across said resistance due to the power source current, and a comparitor for comparing the voltage generated across said resistance with a predetermined voltage, said comparitor producing said voltage pulse when the voltage generated across said resistance exceeds said predetermined voltage.
Claim 29
Dependent Claim
16 words
The apparatus according to claim 24, wherein said resistance is external to the semiconductor integrated circuit.
Claim 30
Dependent Claim
35 words
The apparatus according to claim 24, wherein said resistance is connected in series with the power input terminal of the semiconductor integrated circuit such that all of the power source current passes through said resistance.
Claim 31
Dependent Claim
52 words
The apparatus according to claim 24, wherein the semiconductor integrated circuit is part of said apparatus and is a CMOS inverter including a P-channel MOS transistor having a source, and said power input terminal is connected to said source of said P-channel transistor, said power input terminal for receiving a positive voltage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-01 | 2001-12-01 | 2002-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-01 | 2005-12-01 | 2006-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-01 | 2009-12-01 | 2010-06-02 | $7700.00 | Window Closed / Lapsed |