Process for making doped polysilicon layers on sidewalls

Claim 2

Method for creating a doped polysilicon layer of accurate shape on a sidewall of a semiconductor structure, comprising the steps of: (a) depositing a polysilicon film covering at least part of said semiconductor structure and of said sidewall, (b) doping said polysilicon film, (c) etching said polysilicon film using a reactive ion etching (RIE) process using reactive ion etching parameters providing for a high etch rate of said polysilicon film in order to define the approximate shape of said polysilicon layer on said sidewall, and (d) etching said polysilicon layer using a low polysilicon etch rate reactive ion etching process applying a high bias voltage such that non-uniformities of the surface of said polysilicon layer are removed by sputtering.

Claim 3

Method of claim 1, wherein the first and second steps (a) and (b) are carried out concurrently, i.e., wherein said polysilicon film is doped while being deposited.

Claim 4

Method of claim 1, wherein at least one of the following species, or any combination thereof, is used for the first reactive ion etching process step (a): Cl, Br, C, Ar, F, and He.

Claim 5

Method of claim 3, wherein a plasma is used which comprises: Cl 2 , HBr, He, CHF 3 , or CF 4 and Ar.

Claim 6

Method of claim 1, wherein the first reactive ion etch step (a) is stopped before said polysilicon film is completely removed from surfaces other than said sidewall, thus leaving a thin layer of polysilicon on these surfaces, and wherein a third reactive ion etch step is carried out after the second reactive ion etch step (b), to remove said thin layer of polysilicon from surfaces other than said sidewall.

Claim 7

Method of claim 5, wherein essentially the same reactive ion etching parameters are used for the third reactive ion etch step as were used for the first reactive ion etch step (a).

Claim 8

Method of claim 1, wherein the bias voltage, which is one of said reactive ion etching parameters used for the first reactive ion etching process step (a), is approximately 800V.

Claim 9

Method of claim 1, wherein at least one of the following species, or any combination thereof, is used for the second reactive ion etching process step (b): Cl, Br, C, Ar, or F.

Claim 10

Method of claim 1, wherein an appropriate mask is placed or formed on top of said semiconductor structure before said first reactive ion etching process step (a) is carried out, said mask protecting those portions which are not to be attacked.

Claim 11

Method of claim 1, wherein said first reactive ion etching process step (a) is a maskless process, said reactive ion etching parameters being chosen such that said polysilicon film is etch anisotropically.

Claim 12

Method of claim 5, wherein said first and second reactive ion etching process steps (a) and (b), and said third reactive ion etching process are carried out in the same processing chamber.

Claim 13

Method of claim 1, wherein said semiconductor structure is a partially processed semiconductor device.

Claim 14

Method of claim 1, wherein said semiconductor structure is a partially processed micromechanical device.

Claim 15

Method of claim 1, wherein said polysilicon layer on said sidewall is part of a semiconductor device, such as a vertical field-effect transistor (FET).

Claim 16

Method of claim 1, wherein said reactive ion etching parameters are chosen such that the selectivity of polysilicon to said semiconductor structure is at least 5.

Claim 17

Method of claim 1, wherein said sidewall is a sidewall of a depression or trench.

Claim 18

Method of claim 1, wherein said sidewall is a sidewall of an elevation, berm, or ridge.

Claim 19

Method of claim 1, wherein said semiconductor structure is a partially processed random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), or programmable logic array (PLA).

Claim 20

Method for making a vertical field effect transistor in a substrate, comprising the steps: (a) defining a source electrode in said substrate by means of doping, (b) forming a vertical gate channel, (c) forming a drain electrode on the end of said gate channel being opposite to the end where said source electrode is situated, (d) providing a thin gate oxide on the sidewalls of said gate channel, (e) depositing a polysilicon film covering part of said substrate and part of said thin gate oxide on said sidewall, (f) doping said polysilicon film, (g) etching said polysilicon film using a reactive ion etching (RIE) process using reactive ion etching parameters providing for a high etch rate of said polysilicon film in order to define the approximate shape of said polysilicon layer on said thin gate oxide, said reactive ion etching process being stopped before said polysilicon film is completely removed from surfaces other than said sidewall, thus leaving a thin polysilicon layer on these surfaces, (h) etching said polysilicon layer using a low polysilicon etch rate reactive ion etching process applying a high bias voltage such that non-uniformities of the surface of said polysilicon layer are removed by sputtering, (i) etching said polysilicon film using a reactive ion etching process to remove thin polysilicon layer on said surfaces other than said sidewall.

Claim 21

Method for making a vertical field effect transistor in a substrate, comprising the steps: (a) defining a source electrode in said substrate by means of doping, (b) forming a vertical gate channel, (c) forming a drain electrode on the end of said gate channel being opposite to the end where said source electrode is situated, (d) providing a thin gate oxide on the sidewalls of said gate channel, (e) depositing a polysilicon film covering part of said substrate and part of said thin gate oxide on said sidewall, (f) doping said polysilicon film, (g) etching said polysilicon film using a reactive ion etching (RIE) process using reactive ion etching parameters providing for a high etch rate of said polysilicon film in order to define the approximate shape of said polysilicon layer on said thin gate oxide, said reactive ion etching process being stopped before said polysilicon film is completely removed from surfaces other than said sidewall, thus leaving a thin polysilicon layer on these surfaces, (h) etching said polysilicon layer using a low polysilicon etch rate reactive ion etching process applying a high bias voltage such that non-uniformities of the surface of said polysilicon layer are removed by sputtering, (i) etching said polysilicon film using a reactive ion etching process to remove thin polysilicon layer on said surfaces other than said sidewall.

Claim 22

Method of claim 19, wherein the steps (e) and (f) are carried out concurrently, i.e., wherein said polysilicon film is doped while being deposited.

Claim 23

Method of claim 19, wherein said first reactive ion etching process step (g) is a maskless process, said reactive ion etching parameters being chosen such that said polysilicon film is etch anisotropically.