Method for forming a DRAM capacitor using HSG-Si

Claim 1

A method for forming a capacitor of a dynamic random access memory cell, said method comprising: forming a dielectric layer over a substrate; forming and patterning a first photoresist layer on the dielectric layer, said first photoresist layer defining a contact area over a portion of the substrate surface; removing a portion of the dielectric layer left uncovered by said first photoresist layer to form a first trench, thereby exposing said portion of the substrate surface; forming a polysilicon layer over the dielectric layer, wherein said polysilicon layer fills in said first trench and covers at least a portion of the dielectric layer surrounding said first trench; forming a hemispherical-grained silicon (HSG-Si) layer on the polysilicon layer, said HSG-Si layer comprising a plurality of silicon grains spaced apart, wherein portions of the polysilicon layer between said silicon grains remain uncovered by said HSG-Si layer; implanting particles into the polysilicon layer using said plurality of silicon grains as a mask, thereby forming a plurality of particle regions in the polysilicon layer, wherein said particles cause said particle regions to have an increased resistance to oxidation; removing said HSG-Si layer; thermally oxidizing the polysilicon layer using said plurality of particle regions as an anti-oxidation mask, thereby forming a plurality of polysilicon-oxide regions in the polysilicon layer; removing said plurality of particle regions and portions of the polysilicon layer left uncovered by said plurality of polysilicon-oxide regions, thereby forming a plurality of second trenches in the polysilicon layer; removing said plurality of polysilicon-oxide regions; forming and patterning a second photoresist layer on the polysilicon layer, wherein said second photoresist layer defines on said polysilicon layer a storage node aligned with the first trench; and removing portions of the polysilicon layer left uncovered by said second photoresist layer to form a storage node, said storage node serving as a bottom electrode of the capacitor of the dynamic random access memory.

Claim 2

A method for forming a capacitor of a dynamic random access memory cell, said method comprising: forming a dielectric layer over a substrate; forming and patterning a first photoresist layer on the dielectric layer, said first photoresist layer defining a contact area over a portion of the substrate surface; removing a portion of the dielectric layer left uncovered by said first photoresist layer to form a first trench, thereby exposing said portion of the substrate surface; forming a polysilicon layer over the dielectric layer, wherein said polysilicon layer fills in said first trench and covers at least a portion of the dielectric layer surrounding said first trench; forming a hemispherical-grained silicon (HSG-Si) layer on the polysilicon layer, said HSG-Si layer comprising a plurality of silicon grains spaced apart, wherein portions of the polysilicon layer between said silicon grains remain uncovered by said HSG-Si layer; implanting particles into the polysilicon layer using said plurality of silicon grains as a mask, thereby forming a plurality of particle regions in the polysilicon layer, wherein said particles cause said particle regions to have an increased resistance to oxidation; removing said HSG-Si layer; thermally oxidizing the polysilicon layer using said plurality of particle regions as an anti-oxidation mask, thereby forming a plurality of polysilicon-oxide regions in the polysilicon layer; removing said plurality of particle regions and portions of the polysilicon layer left uncovered by said plurality of polysilicon-oxide regions, thereby forming a plurality of second trenches in the polysilicon layer; removing said plurality of polysilicon-oxide regions; forming and patterning a second photoresist layer on the polysilicon layer, wherein said second photoresist layer defines on said polysilicon layer a storage node aligned with the first trench; and removing portions of the polysilicon layer left uncovered by said second photoresist layer to form a storage node, said storage node serving as a bottom electrode of the capacitor of the dynamic random access memory.

Claim 11

A method for forming a capacitor of a dynamic random access memory cell, said method comprising: forming a oxide layer over a substrate; planarizing the oxide layer; forming and patterning a first photoresist layer on the oxide layer, said first photoresist layer defining a contact area over a portion of the substrate surface; removing a portion of the dielectric layer left uncovered by said first photoresist layer to form a first trench, thereby exposing said portion of the substrate surface; forming a doped polysilicon layer over the oxide layer, wherein said first trench in the oxide layer is filled by the doped polysilicon layer; forming a hemispherical-grained silicon (HSG-Si) layer on the doped polysilicon layer, said HSG-Si layer comprising a plurality of silicon grains spaced apart, wherein portions of the doped polysilicon layer between said silicon grains remain uncovered by said HSG-Si layer; implanting nitrogen atoms in the doped polysilicon layer using said plurality of silicon grains as an implant mask, thereby forming a plurality of nitrogen regions in the doped polysilicon layer; removing said HSG-Si layer; thermally oxidizing the doped polysilicon layer using said plurality of nitrogen regions as an anti-oxidation mask, thereby forming a plurality of polysilicon-oxide regions in the doped polysilicon layer; removing said plurality of nitrogen regions and portions of the doped polysilicon layer left uncovered by said plurality of polysilicon-oxide regions, thereby forming a plurality of second trenches in the doped polysilicon layer; removing said plurality of polysilicon-oxide regions; forming and patterning a second photoresist layer on the doped polysilicon layer, said second photoresist layer defining a storage node aligned with said first trench over a portion of said doped polysilicon layer; and removing portions of the doped polysilicon layer left uncovered by the second photoresist layer to form a storage node, said storage node serving as a bottom electrode of the capacitor of the dynamic random access memory.

Claim 12

A method for forming a capacitor of a dynamic random access memory cell, said method comprising: forming a oxide layer over a substrate; planarizing the oxide layer; forming and patterning a first photoresist layer on the oxide layer, said first photoresist layer defining a contact area over a portion of the substrate surface; removing a portion of the dielectric layer left uncovered by said first photoresist layer to form a first trench, thereby exposing said portion of the substrate surface; forming a doped polysilicon layer over the oxide layer, wherein said first trench in the oxide layer is filled by the doped polysilicon layer; forming a hemispherical-grained silicon (HSG-Si) layer on the doped polysilicon layer, said HSG-Si layer comprising a plurality of silicon grains spaced apart, wherein portions of the doped polysilicon layer between said silicon grains remain uncovered by said HSG-Si layer; implanting nitrogen atoms in the doped polysilicon layer using said plurality of silicon grains as an implant mask, thereby forming a plurality of nitrogen regions in the doped polysilicon layer; removing said HSG-Si layer; thermally oxidizing the doped polysilicon layer using said plurality of nitrogen regions as an anti-oxidation mask, thereby forming a plurality of polysilicon-oxide regions in the doped polysilicon layer; removing said plurality of nitrogen regions and portions of the doped polysilicon layer left uncovered by said plurality of polysilicon-oxide regions, thereby forming a plurality of second trenches in the doped polysilicon layer; removing said plurality of polysilicon-oxide regions; forming and patterning a second photoresist layer on the doped polysilicon layer, said second photoresist layer defining a storage node aligned with said first trench over a portion of said doped polysilicon layer; and removing portions of the doped polysilicon layer left uncovered by the second photoresist layer to form a storage node, said storage node serving as a bottom electrode of the capacitor of the dynamic random access memory.

Claim 18

A method of forming an integrated circuit capacitor structure, the method comprising: forming a polysilicon layer over a substrate; forming a hemispherical-grained silicon (HSG-Si) layer on the polysilicon layer, said HSG-Si layer comprising a plurality of silicon grains spaced apart, wherein portions of the polysilicon layer between said silicon grains remain uncovered by said HSG-Si layer; implanting nitrogen atoms in the polysilicon layer using said plurality of silicon grains as an implant mask, thereby forming a plurality of nitrogen regions in the polysilicon layer; removing said HSG-Si layer; thermally oxidizing the polysilicon layer using said plurality of nitrogen regions as an anti-oxidation mask, thereby forming a plurality of polysilicon-oxide regions in the polysilicon layer; removing said plurality of nitrogen regions and portions of the polysilicon layer beneath said nitrogen regions, thereby forming a plurality of second trenches in the polysilicon layer between said plurality of polysilicon-oxide regions; removing said plurality of polysilicon-oxide regions; and removing portions of the polysilicon layer, wherein a remaining portion of the polysilicon layer forms a bottom electrode of an integrated circuit capacitor.

Claim 19

A method of forming an integrated circuit capacitor structure, the method comprising: forming a polysilicon layer over a substrate; forming a hemispherical-grained silicon (HSG-Si) layer on the polysilicon layer, said HSG-Si layer comprising a plurality of silicon grains spaced apart, wherein portions of the polysilicon layer between said silicon grains remain uncovered by said HSG-Si layer; implanting nitrogen atoms in the polysilicon layer using said plurality of silicon grains as an implant mask, thereby forming a plurality of nitrogen regions in the polysilicon layer; removing said HSG-Si layer; thermally oxidizing the polysilicon layer using said plurality of nitrogen regions as an anti-oxidation mask, thereby forming a plurality of polysilicon-oxide regions in the polysilicon layer; removing said plurality of nitrogen regions and portions of the polysilicon layer beneath said nitrogen regions, thereby forming a plurality of second trenches in the polysilicon layer between said plurality of polysilicon-oxide regions; removing said plurality of polysilicon-oxide regions; and removing portions of the polysilicon layer, wherein a remaining portion of the polysilicon layer forms a bottom electrode of an integrated circuit capacitor.