Method for manufacturing semiconductor device incorporating DRAM section and logic circuit section

Claim 1

A method for manufacturing a semiconductor device incorporating a memory section and a circuit section, comprising the steps of: forming first and second gate electrodes made of a conductive layer on a semiconductor substrate in said memory section and said circuit section, respectively; introducing first impurities into semiconductor substrate using said first and second gate electrodes as a mask, to form first and second pairs of impurity diffusion regions within said semiconductor substrate in said memory section and said circuit section, respectively; forming a first insulating layer and perforating a first contact hole in said first insulating layer on one of said first pair of impurity diffusion regions; forming a polycrystalline silicon layer on said first insulating layer and patterning said polycrystalline silicon layer to form a bit line connected via said first contact hole to said one of said first pair of impurity diffusion regions; exposing said second gate electrode and said second pair of impurity diffusion regions; forming a refractory metal layer to cover at least said bit line said second gate electrode and said second pair of impurity diffusion regions; performing a heating operation upon said refractory metal layer, so that metal silicide layers are formed in said bit line, said second gate electrode and said second pair of impurity diffusion regions; and removing unreacted portions of said refractory metal layer.

Claim 2

A method for manufacturing a semiconductor device incorporating a memory section and a circuit section, comprising the steps of: forming first and second gate electrodes made of a conductive layer on a semiconductor substrate in said memory section and said circuit section, respectively; introducing first impurities into semiconductor substrate using said first and second gate electrodes as a mask, to form first and second pairs of impurity diffusion regions within said semiconductor substrate in said memory section and said circuit section, respectively; forming a first insulating layer and perforating a first contact hole in said first insulating layer on one of said first pair of impurity diffusion regions; forming a polycrystalline silicon layer on said first insulating layer and patterning said polycrystalline silicon layer to form a bit line connected via said first contact hole to said one of said first pair of impurity diffusion regions; exposing said second gate electrode and said second pair of impurity diffusion regions; forming a refractory metal layer to cover at least said bit line said second gate electrode and said second pair of impurity diffusion regions; performing a heating operation upon said refractory metal layer, so that metal silicide layers are formed in said bit line, said second gate electrode and said second pair of impurity diffusion regions; and removing unreacted portions of said refractory metal layer.

Claim 8

A method for manufacturing a semiconductor device incorporating a memory section and a circuit section, comprising the steps of: forming first and second gate electrodes made of a conductive layer on a semiconductor substrate in said memory section and said circuit section, respectively; introducing first impurities into semiconductor substrate using said first and second gate electrodes as a mask, to form first and second pairs of impurity diffusion regions within said semiconductor substrate in said memory section and said circuit section, respectively; forming a first insulating layer on said first and second gate electrodes; etching pack said first insulating layer to form first sidewall insulating layers on sidewalls of said first and second electrodes; forming a first photoresist pattern layer to cover said circuit section; introducing second impurities into said semiconductor substrate using said first photoresist pattern layer, said first gate electrode and said first sidewall insulating layers as a mask, to form a third pair of impurity diffusion regions in said memory section; forming a second insulating layer and perforating a first contact hole in said second insulating layer on one of said third pair of impurity diffusion regions; forming a polycrystalline silicon layer on said second insulating layer and patterning said polycrystalline silicon layer to form a bit line connected via said first contact hole to said one of said third pair of impurity diffusion regions; forming a second photoresist pattern layer to cover said memory section; etching back said second insulating layer using said second photoresist pattern layer as a mask to form a second sidewall insulating layer on said first sidewall insulating layer of said second gate electrode; introducing third impurities into said semiconductor substrate using said second photoresist pattern layer, said second gate electrode and said second sidewall insulating layer as a mask, to form a fourth pair of impurity diffusion regions in said circuit section; exposing said second gate electrode and said fourth pair of impurity diffusion regions; forming a refractory metal layer to cover at least said bit line said second gate electrode and said fourth pair of impurity diffusion regions; performing a heating operation upon said refractory metal layer, so that metal silicide layers are formed in said bit line, said second gate electrode and said fourth pair of impurity diffusion regions; and removing unreacted portions of said refractory metal layer.

Claim 9

A method for manufacturing a semiconductor device incorporating a memory section and a circuit section, comprising the steps of: forming first and second gate electrodes made of a conductive layer on a semiconductor substrate in said memory section and said circuit section, respectively; introducing first impurities into semiconductor substrate using said first and second gate electrodes as a mask, to form first and second pairs of impurity diffusion regions within said semiconductor substrate in said memory section and said circuit section, respectively; forming a first insulating layer on said first and second gate electrodes; etching pack said first insulating layer to form first sidewall insulating layers on sidewalls of said first and second electrodes; forming a first photoresist pattern layer to cover said circuit section; introducing second impurities into said semiconductor substrate using said first photoresist pattern layer, said first gate electrode and said first sidewall insulating layers as a mask, to form a third pair of impurity diffusion regions in said memory section; forming a second insulating layer and perforating a first contact hole in said second insulating layer on one of said third pair of impurity diffusion regions; forming a polycrystalline silicon layer on said second insulating layer and patterning said polycrystalline silicon layer to form a bit line connected via said first contact hole to said one of said third pair of impurity diffusion regions; forming a second photoresist pattern layer to cover said memory section; etching back said second insulating layer using said second photoresist pattern layer as a mask to form a second sidewall insulating layer on said first sidewall insulating layer of said second gate electrode; introducing third impurities into said semiconductor substrate using said second photoresist pattern layer, said second gate electrode and said second sidewall insulating layer as a mask, to form a fourth pair of impurity diffusion regions in said circuit section; exposing said second gate electrode and said fourth pair of impurity diffusion regions; forming a refractory metal layer to cover at least said bit line said second gate electrode and said fourth pair of impurity diffusion regions; performing a heating operation upon said refractory metal layer, so that metal silicide layers are formed in said bit line, said second gate electrode and said fourth pair of impurity diffusion regions; and removing unreacted portions of said refractory metal layer.