Method for manufacturing a narrowed sidewall spacer in a peripheral circuit of a ULSI semiconductor memory device

Claim 1

A method for manufacturing an ultra-large-scale integrated memory device having a memory cell array section and a peripheral circuit section, said peripheral circuit section including a plurality of transistors formed therein, the method comprising the steps of: forming an insulating film over the surface of both the memory array section and the peripheral array section; forming an etch blocking film over said insulating film; forming capacitors at select locations of said memory cell array section, said insulating film and said etch blocking film preventing deterioration of the underlying surface structure during said capacitor forming step; removing, after said capacitor forming step, the etch blocking film from the surface of said peripheral array section to expose said insulating film; and forming side wall spacers on the side walls of the gate electrode of said transistors in the peripheral array section by anisotropically etching said insulating film.

Claim 2

A method for manufacturing an ultra-large-scale integrated memory device having a memory cell array section and a peripheral circuit section, said peripheral circuit section including a plurality of transistors formed therein, the method comprising the steps of: forming an insulating film over the surface of both the memory array section and the peripheral array section; forming an etch blocking film over said insulating film; forming capacitors at select locations of said memory cell array section, said insulating film and said etch blocking film preventing deterioration of the underlying surface structure during said capacitor forming step; removing, after said capacitor forming step, the etch blocking film from the surface of said peripheral array section to expose said insulating film; and forming side wall spacers on the side walls of the gate electrode of said transistors in the peripheral array section by anisotropically etching said insulating film.

Claim 6

A method for manufacturing an ultra-large-scale integrated semiconductor memory device, comprising the steps of: forming a first conductive layer provided as a word line in a cell array of said memory device having a first conductive-type substrate and provided as the gate electrode of a transistor in a peripheral circuit section of said memory device, by interposing a gate insulating film on said substrate; forming a lightly doped region of a second conductive type impurity self-aligned to said first conductive layer near the surface of said semiconductor substrate and sequentially laminating a high temperature oxide film and an etch blocking film on the whole resultant surface; forming a cell capacitor in said cell array by forming a contact hole in said laminated film, and sequentially forming a second conductive layer in contact with said lightly doped region of the second conductive type impurity through the contact hole, interposing a capacitor insulating film and covering the second conductive layer with a third conductive layer; forming side wall spacers of said high temperature oxide film on the side walls of said first conductive layer arranged in said peripheral circuit section by removing said etch blocking film after said cell capacitor forming step, and anisotropically etching said high temperature oxide film; and forming a heavily doped region of said second conductive type impurity self-aligned to said side wall spacers near the surface of said semiconductor substrate.

Claim 7

A method for manufacturing an ultra-large-scale integrated semiconductor memory device, comprising the steps of: forming a first conductive layer provided as a word line in a cell array of said memory device having a first conductive-type substrate and provided as the gate electrode of a transistor in a peripheral circuit section of said memory device, by interposing a gate insulating film on said substrate; forming a lightly doped region of a second conductive type impurity self-aligned to said first conductive layer near the surface of said semiconductor substrate and sequentially laminating a high temperature oxide film and an etch blocking film on the whole resultant surface; forming a cell capacitor in said cell array by forming a contact hole in said laminated film, and sequentially forming a second conductive layer in contact with said lightly doped region of the second conductive type impurity through the contact hole, interposing a capacitor insulating film and covering the second conductive layer with a third conductive layer; forming side wall spacers of said high temperature oxide film on the side walls of said first conductive layer arranged in said peripheral circuit section by removing said etch blocking film after said cell capacitor forming step, and anisotropically etching said high temperature oxide film; and forming a heavily doped region of said second conductive type impurity self-aligned to said side wall spacers near the surface of said semiconductor substrate.