Method and apparatus for providing an offset level to an image signal

Claim 2

A black level correction circuit that provides an offset level to an input image signal, the black level correction circuit comprising: a first summing circuit having a first input coupled to an input of the black level correction circuit that receives the input image signal and a second input coupled to the offset level, that adds the offset level to the input image signal and that provides at an output a first summed signal; a first programmable amplifier having an input coupled to the output of the first summing circuit, that amplifies the first summed signal and that provides at an output an output signal; a second summing circuit having a first input coupled to the output of the programmable amplifier and a second input coupled to a reference signal, that sums the output signal and the reference signal and that provides at an output a second summed signal; an integrator having an input coupled to the output of the second summing circuit, that integrates the second summed signal and that provides the offset level at an output that is coupled to the second input of the first summing circuit; and wherein the offset level added to the input image signal biases the first summed signal to one end of the first programmable amplifier's operating range so as to make full use of the first programmable amplifier's total operating range.

Claim 3

The black level correction circuit of claim 1, further comprising a switch disposed between the output of the programmable amplifier and the first input of the second summing circuit, the switch coupling the output signal to the first input of the second summing circuit in response to the input image signal corresponding to a reference pixel present at the input to the black level correction circuit, and the switch decoupling the output signal from the first input of the second summing circuit in response to the input image signal at the input to the black level correction circuit corresponding to an intensity level of a pixel.

Claim 4

The black level correction circuit of claim 1, further comprising a second programmable amplifier having an input coupled to the output of the second summing circuit and an output coupled to the input of the integrator, the second programmable amplifier having a gain that is an inverse of a gain of the first programmable amplifier so as to provide a closed loop constant gain.

Claim 5

The black level correction circuit of claim 1, further comprising a second programmable amplifier having an input coupled to the output of the integrator and an output coupled to the second input of the first summing circuit, the second programmable amplifier having a gain that is an inverse of a gain of the first programmable amplifier so as to provide a closed loop constant gain.

Claim 6

The black level correction circuit of claim 1, wherein the offset level added to the input image signal also biases the output signal to one end of a input dynamic range of an analog-to-digital converter, coupled to the output of the first programmable amplifier, to make full use of the analog-to-digital converter's input dynamic range.

Claim 7

An image acquisition system, comprising: a charge coupled device (CCD) sensor that detects and outputs an analog signal at an output of the CCD sensor; a CCD interface circuit, having an input coupled to the output of the CCD sensor, the CCD interface circuit including: a correlated double-sampling circuit having an input coupled to the input of the CCD interface circuit, that removes any noise or offsets common to at least a first sample and a second sample of the analog signal and that outputs a filtered signal at an output of the correlated double-sampling circuit; a black level correction circuit having a first input coupled to the output of the correlated double sampling circuit and a second input coupled to an offset level signal, that adds the offset level signal to the filtered signal and that provides an output signal at an output of the black level correction circuit, the black level correction circuit comprising: a first summing circuit having a first input coupled to the input of the black level correction circuit that receives the filtered signal and a second input coupled to the offset level signal, that adds the offset level signal to the filtered signal and that provides a first summed signal to an output of the first summing circuit; a first programmable amplifier having an input coupled to the output of the first summing circuit, that amplifies the first summed signal and that provides at an output the output signal; a second summing circuit having a first input coupled to the output of the programmable amplifier and a second input coupled to a reference signal, that sums the output signal and the reference signal and that provides at an output a second summed signal; an integrator having an input coupled to the output of the second summing circuit, that integrates the second summed signal and that provides the offset level signal at an output that is coupled to the second input of the first summing circuit; and wherein the offset level added to the filtered signal biases the first summed signal to one end of the first programmable amplifier's operating range to make full use of the first programmable amplifier's operating range.

Claim 8

An image acquisition system, comprising: a charge coupled device (CCD) sensor that detects and outputs an analog signal at an output of the CCD sensor; a CCD interface circuit, having an input coupled to the output of the CCD sensor, the CCD interface circuit including: a correlated double-sampling circuit having an input coupled to the input of the CCD interface circuit, that removes any noise or offsets common to at least a first sample and a second sample of the analog signal and that outputs a filtered signal at an output of the correlated double-sampling circuit; a black level correction circuit having a first input coupled to the output of the correlated double sampling circuit and a second input coupled to an offset level signal, that adds the offset level signal to the filtered signal and that provides an output signal at an output of the black level correction circuit, the black level correction circuit comprising: a first summing circuit having a first input coupled to the input of the black level correction circuit that receives the filtered signal and a second input coupled to the offset level signal, that adds the offset level signal to the filtered signal and that provides a first summed signal to an output of the first summing circuit; a first programmable amplifier having an input coupled to the output of the first summing circuit, that amplifies the first summed signal and that provides at an output the output signal; a second summing circuit having a first input coupled to the output of the programmable amplifier and a second input coupled to a reference signal, that sums the output signal and the reference signal and that provides at an output a second summed signal; an integrator having an input coupled to the output of the second summing circuit, that integrates the second summed signal and that provides the offset level signal at an output that is coupled to the second input of the first summing circuit; and wherein the offset level added to the filtered signal biases the first summed signal to one end of the first programmable amplifier's operating range to make full use of the first programmable amplifier's operating range.

Claim 9

The image acquisition system of claim 6, further comprising an analog-to-digital converter having an input coupled to the output of the black level correction circuit, that converts the output signal to a digital signal and that outputs the digital signal at an output of the analog-to-digital converter; and wherein the offset level added to the filtered signal also biases the output signal to one end of the analog-to-digital converter's input dynamic range to make full use of the analog-to-digital converter's input dynamic range.

Claim 10

The image acquisition system of claim 6, further comprising a switch disposed between the output of the programmable amplifier and the first input of the second summing circuit, the switch coupling the output signal to the first input of the second summing circuit in response to the filtered signal corresponding to a reference pixel present at the input to the black level correction circuit, and the switch decoupling the output signal from the first input of the second summing circuit in response to the input signal at the input to the black level correction circuit corresponding to an image signal.

Claim 11

The image acquisition system of claim 6, further comprising a second programmable amplifier having an input coupled to the output of the second summing circuit and an output coupled to the input of the integrator, the second programmable amplifier having a gain that is an inverse of a gain of the first programmable amplifier so as to provide a closed loop constant gain.

Claim 12

The image acquisition system of claim 6, further comprising a second programmable amplifier having an input coupled to the output of the integrator and an output coupled to the second input of the first summing circuit, the second programmable amplifier having a gain that is an inverse of a gain of the first programmable amplifier so as to provide a closed loop constant gain.

Claim 13

An integrated circuit, comprising: a first correlated double sampling circuit having a first input and a first output, the first correlated double sampling circuit taking a first sample of an analog signal at the first input, taking a second sample of the analog signal at the first input and taking a difference between the first sample and the second sample to provide a first filtered signal at the first output; a second correlated double sampling circuit having a second input coupled to the first input and a second output, the second correlated double sampling circuit taking a third sample of the analog signal at the first input and a fourth sample of the analog signal at the first input and taking a difference between the third sample and the fourth sample to provide a second filtered signal at the second output; a first summing circuit having a first input coupled to the first output and a second input coupled to a first offset level that sums the first filtered signal and the first offset level and provides at an output a first summed signal; a second summing circuit having a first input coupled to the second output and a second input coupled to a second offset level that sums the second filtered signal with the second offset level and provides at an output a second summed signal; a first switching circuit having a first input coupled to the output of the first summing circuit, a second input coupled to the output of the second summing circuit, that alternately provides a differential first selected signal as one of the first summed signal and the second summed signal to an output of the first switching circuit; a first programmable amplifier having an input coupled to the output of the first switching circuit that amplifies the differential first selected signal and provides an output signal at an output of the first programmable amplifier; a second switching circuit having an input coupled to the output of the first programmable amplifier, that alternately provides the output signal as a second selected signal to one of a first output and a second output of the second switching circuit; a third summing circuit having a first input coupled to the first output of the second switching circuit and a second input coupled to a reference signal, that sums the second selected signal with the reference signal and that provides a third summed signal at an output of the third summing circuit; a fourth summing circuit having a first input coupled to the second output of the second switching circuit and a second input coupled to the reference signal, that sums the second selected signal with the reference signal and that provides a fourth summed signal at an output of the fourth summing circuit; a first integration circuit having an input coupled to the output of the third summing circuit, that integrates the third summed signal and that provides at an output, coupled to the second input of the first summing circuit, a first integrated signal as the first offset level; a second integration circuit having an input coupled to the output of the fourth summing circuit, that integrates the fourth summed signal and that provides at an output, coupled to the second input of the second summing circuit, a second integrated signal as the second offset level.

Claim 14

An integrated circuit, comprising: a first correlated double sampling circuit having a first input and a first output, the first correlated double sampling circuit taking a first sample of an analog signal at the first input, taking a second sample of the analog signal at the first input and taking a difference between the first sample and the second sample to provide a first filtered signal at the first output; a second correlated double sampling circuit having a second input coupled to the first input and a second output, the second correlated double sampling circuit taking a third sample of the analog signal at the first input and a fourth sample of the analog signal at the first input and taking a difference between the third sample and the fourth sample to provide a second filtered signal at the second output; a first summing circuit having a first input coupled to the first output and a second input coupled to a first offset level that sums the first filtered signal and the first offset level and provides at an output a first summed signal; a second summing circuit having a first input coupled to the second output and a second input coupled to a second offset level that sums the second filtered signal with the second offset level and provides at an output a second summed signal; a first switching circuit having a first input coupled to the output of the first summing circuit, a second input coupled to the output of the second summing circuit, that alternately provides a differential first selected signal as one of the first summed signal and the second summed signal to an output of the first switching circuit; a first programmable amplifier having an input coupled to the output of the first switching circuit that amplifies the differential first selected signal and provides an output signal at an output of the first programmable amplifier; a second switching circuit having an input coupled to the output of the first programmable amplifier, that alternately provides the output signal as a second selected signal to one of a first output and a second output of the second switching circuit; a third summing circuit having a first input coupled to the first output of the second switching circuit and a second input coupled to a reference signal, that sums the second selected signal with the reference signal and that provides a third summed signal at an output of the third summing circuit; a fourth summing circuit having a first input coupled to the second output of the second switching circuit and a second input coupled to the reference signal, that sums the second selected signal with the reference signal and that provides a fourth summed signal at an output of the fourth summing circuit; a first integration circuit having an input coupled to the output of the third summing circuit, that integrates the third summed signal and that provides at an output, coupled to the second input of the first summing circuit, a first integrated signal as the first offset level; a second integration circuit having an input coupled to the output of the fourth summing circuit, that integrates the fourth summed signal and that provides at an output, coupled to the second input of the second summing circuit, a second integrated signal as the second offset level.

Claim 15

The integrated circuit of claim 11, further comprising a second programmable amplifier having an input coupled to the output of the first integration circuit and an output coupled to the second input of the first summing circuit, the second programmable amplifier having a gain that is an inverse of a gain of the first programmable amplifier so as to provide a closed loop constant gain.

Claim 16

The integrated circuit of claim 12, further comprising a third programmable amplifier having an input coupled to the output of the second integration circuit and an output coupled to the second input of the second summing circuit, the third programmable amplifier having a gain that is an inverse of a gain of the first programmable amplifier so as to provide a closed loop constant gain.

Claim 17

The integrated circuit of claim 11, further comprising a second programmable amplifier having an input coupled to the output of the third summing circuit and an output coupled to the input of the first integration circuit, the second programmable amplifier having a gain that is an inverse of a gain of the first programmable amplifier so as to provide a closed loop constant gain.

Claim 18

The integrated circuit of claim 14, further comprising a third programmable amplifier having an input coupled to the output of the fourth summing circuit and an output coupled to the input of the second integration circuit, the third programmable amplifier having a gain that is an inverse of the gain of the first programmable amplifier so as to provide a closed loop constant gain.