Patent US5754802A successfully refreshed from Google Patents.
US5754802A
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Increasing data transfer efficiency for a read operation in a non-split transaction bus environment by substituting a write operation for the read operation
Assignee: Hitachi Ltd
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Filing: 1996-05-15
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Granted: 1998-05-19
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Expires: 2016-05-15
Abstract
Abstract A method and apparatus for increasing data transfer efficiency for a read operation in a non-split transaction bus environment by substituting a write operation for the read operation. The data transfer efficiency is increased and deadlocking is reduced by substituting two write operations (one from an I/O device to a bus controller and the other from the bus controller to the I/O device) for one read operation. Further, the present invention improves the efficiency of data transfer by maintaining the compatibility of a bus specification when DMA of an I/O bus having no split transfer function, such as a PCI bus or inter-I/O transfer, is executed. A processor instructs a data transfer operation to an I/O device or bus conversion adapter. The I/O device or bus conversion adapter connected to a bus outputs a write access, and a bus connection controller connected to the bus receives the write access and reads data in a main memory. The bus connection controller then transfers read data to the I/O device or the bus conversion adapter. Such an operation may also be performed between two I/O devices or bus conversion adapters.
Inventors
- 👤 Koichi Okazawa
- 👤 Hideki Osaka
- 👤 Kenichi Saitou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:22
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4221; G06F13/423; G06F13/10; G06F13/12; G06F13/124; G06F13/126; G06F13/40; G06F13/4004; G06F13/4027; G06F13/4031; G06F13/4036
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
304 words
A data transfer system for transmitting data between modules connected by a bus, comprising: a main memory; a processor bus connected to said memory; a bus connection controller connected to said processor bus; a system bus connected to said bus connection controller; an I/O device connected to said system bus, said I/O device executing a write access to said bus connection controller via said system bus; said bus connection controller receiving said write access, reading data from said main memory, and executing said write access so as to transfer said data to said I/O device, said bus connection controller including a storage portion for storing said data outputted by said write access; a processor connected to said processor bus, said processor issuing an operation instruction to said I/O device, and said I/O device executing said write access to said bus connection controller according to said operation instruction; said data outputted by said write access including: a request address indicating the address of said storage portion of said bus connection controller, a read address indicating the address where said bus connection controller reads said data from said main memory, and a return address indicating the address where said data transferred to said I/O device from said bus connection controller is stored; said bus connection controller further including: a request queue for queuing said write access to said bus connection controller, and a first request register for setting an address of said request queue by said request address; and said I/O device including: a second request address setting register for setting a request address which is the address of said request queue to which said write access to said bus connection controller is executed, and a return address setting register for setting an address indicating the destination of said data outputted by said bus connection controller.
Claim 2
Dependent Claim
304 words
A data transfer system for transmitting data between modules connected by a bus, comprising: a main memory; a processor bus connected to said memory; a bus connection controller connected to said processor bus; a system bus connected to said bus connection controller; an I/O device connected to said system bus, said I/O device executing a write access to said bus connection controller via said system bus; said bus connection controller receiving said write access, reading data from said main memory, and executing said write access so as to transfer said data to said I/O device, said bus connection controller including a storage portion for storing said data outputted by said write access; a processor connected to said processor bus, said processor issuing an operation instruction to said I/O device, and said I/O device executing said write access to said bus connection controller according to said operation instruction; said data outputted by said write access including: a request address indicating the address of said storage portion of said bus connection controller, a read address indicating the address where said bus connection controller reads said data from said main memory, and a return address indicating the address where said data transferred to said I/O device from said bus connection controller is stored; said bus connection controller further including: a request queue for queuing said write access to said bus connection controller, and a first request register for setting an address of said request queue by said request address; and said I/O device including: a second request address setting register for setting a request address which is the address of said request queue to which said write access to said bus connection controller is executed, and a return address setting register for setting an address indicating the destination of said data outputted by said bus connection controller.
Claim 3
Dependent Claim
52 words
A data transfer system according to claim 1, wherein upon receipt of a read access request from said I/O device, said system bus is occupied by said read access request during a period from said read access request until output of data according to said read access request to said I/O device.
Claim 4
Dependent Claim
47 words
A data transfer system according to claim 1, wherein said bus connection controller executes a read access to said main memory by said read address outputted as write access data from said I/O device and stores the return address for said I/O device in said request queue.
Claim 5
Dependent Claim
44 words
A data transfer system according to claim 3, wherein when an error occurs in said read access request to said main memory, said bus connection controller assigns an error code to a return address indicating the address of write access to said I/O device.
Claim 6
Dependent Claim
17 words
A data transfer system according to claim 1, wherein said I/O device is a bus conversion adapter.
Claim 7
Dependent Claim
355 words
A data transfer system for transmitting data between modules connected by a bus, comprising: a processor bus; a first and a second bus connection controller connected to said processor bus; a first system bus connected to said first bus connection controller and a second system bus connected to said second bus connection controller; a first I/O device connected to said first system bus and a second I/O device connected to said second system bus, said first I/O device executing a write access to said first bus connection controller via said first system bus; said first bus connection controller receiving said write access from said first I/O device, reading data from said second I/O device via said processor bus and said second bus connection controller, and executing said write access so as to transfer said data of said second I/O device to said first I/O device, said first bus connection controller including a storage portion for storing said data outputted by said write access; a processor connected to said processor bus, said processor issuing an operation instruction to said first I/O device, and said first I/O device executing said write access to said first bus connection controller according to said operation instruction; said data outputted by said write access including: a request address indicating the address of said storage portion of said first bus connection controller, a read address indicating the address where said first bus connection controller reads said data from said second I/O device, and a return address indicating the address where data transferred to said first I/O device from said first bus connection controller is stored; said first I/O device including: a first request address setting register for setting a request address which is the address of a request queue to which said write access to said bus connection controller is executed, and a return address setting register for setting an address indicating the destination of said data outputted by said first bus connection controller; and said second I/O device including: a second request address setting register for setting a second request address for discriminating said write access from said first I/O device.
Claim 8
Dependent Claim
355 words
A data transfer system for transmitting data between modules connected by a bus, comprising: a processor bus; a first and a second bus connection controller connected to said processor bus; a first system bus connected to said first bus connection controller and a second system bus connected to said second bus connection controller; a first I/O device connected to said first system bus and a second I/O device connected to said second system bus, said first I/O device executing a write access to said first bus connection controller via said first system bus; said first bus connection controller receiving said write access from said first I/O device, reading data from said second I/O device via said processor bus and said second bus connection controller, and executing said write access so as to transfer said data of said second I/O device to said first I/O device, said first bus connection controller including a storage portion for storing said data outputted by said write access; a processor connected to said processor bus, said processor issuing an operation instruction to said first I/O device, and said first I/O device executing said write access to said first bus connection controller according to said operation instruction; said data outputted by said write access including: a request address indicating the address of said storage portion of said first bus connection controller, a read address indicating the address where said first bus connection controller reads said data from said second I/O device, and a return address indicating the address where data transferred to said first I/O device from said first bus connection controller is stored; said first I/O device including: a first request address setting register for setting a request address which is the address of a request queue to which said write access to said bus connection controller is executed, and a return address setting register for setting an address indicating the destination of said data outputted by said first bus connection controller; and said second I/O device including: a second request address setting register for setting a second request address for discriminating said write access from said first I/O device.
Claim 9
Dependent Claim
18 words
A data transfer system according to claim 6, wherein said first I/O device is a bus conversion adapter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-18 | 2001-11-17 | 2002-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-18 | 2005-11-17 | 2006-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-18 | 2009-11-17 | 2010-05-19 | $7700.00 | Window Closed / Lapsed |