Patent US5753526A successfully refreshed from Google Patents.
US5753526A
Expired / Lapsed
US
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Manufacturing process of a semiconductor memory device including a trench capacitor and a surrounding gate transistor
Assignee: Toshiba Corp
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Filing: 1996-02-20
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Granted: 1998-05-19
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Expires: 2016-02-20
Abstract
Abstract A method of manufacturing process of a semiconductor device, including the steps of forming a plurality of first trenches in a checkered configuration in a substrate, each of the first trenches having an opening; introducing a first conductivity type impurity from a surface of the substrate so as to form a first conductivity type well in a upper portion of the substrate; forming a capacitor insulating film on a surface of each of the first trenches and burying a storage electrode in each of the first trenches so as to form a trench capacitor in each of the first trenches; burying a first silicon film on each of the storage electrodes of the trench capacitors in the first trenches, etching back each of portions of the first silicon film and removing each of portions of the capacitor insulating films so as to expose portions of side surfaces of the first conductivity type well facing the first trenches; burying a second silicon film doped with a second conductivity type impurity in each of concave portions surrounded by the first silicon films and exposing side surfaces of the first conductivity type well facing the first trenches, and introducing second conductivity type impurities to the first conductivity type well so as to form source regions; and burying a first insulation material on the first and second silicon films in each of the first trenches.
Inventors
- 👤 Tohru Ozaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 16:47
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/0383
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
245 words
A manufacturing process of a semiconductor memory device, comprising: a step of forming a plurality of first trenches in a checkered configuration in a substrate, each of said first trenches having an opening; a step of introducing a first conductivity type impurity from a surface of the substrate so as to form a first conductivity type well in a upper portion of the substrate; a step of forming a capacitor insulating film on a surface of each of the first trenches and burying a storage electrode in each of the first trenches so as to form a trench capacitor in each of the first trenches; a step of burying a first silicon film on each of the storage electrodes of the trench capacitors in the first trenches, etching back each of portions of the first silicon film and removing each of portions of the capacitor insulating films so as to expose portions of side surfaces of the first conductivity type well facing the first trenches; a step of burying a second silicon film doped with a second conductivity type impurity in each of concave portions surrounded by the first silicon films and exposing side surfaces of the first conductivity type well facing the first trenches, and introducing second conductivity type impurities to the first conductivity type well so as to form source regions; and a step of burying a first insulation material on the first and second silicon films in each of the first trenches.
Claim 2
Dependent Claim
245 words
A manufacturing process of a semiconductor memory device, comprising: a step of forming a plurality of first trenches in a checkered configuration in a substrate, each of said first trenches having an opening; a step of introducing a first conductivity type impurity from a surface of the substrate so as to form a first conductivity type well in a upper portion of the substrate; a step of forming a capacitor insulating film on a surface of each of the first trenches and burying a storage electrode in each of the first trenches so as to form a trench capacitor in each of the first trenches; a step of burying a first silicon film on each of the storage electrodes of the trench capacitors in the first trenches, etching back each of portions of the first silicon film and removing each of portions of the capacitor insulating films so as to expose portions of side surfaces of the first conductivity type well facing the first trenches; a step of burying a second silicon film doped with a second conductivity type impurity in each of concave portions surrounded by the first silicon films and exposing side surfaces of the first conductivity type well facing the first trenches, and introducing second conductivity type impurities to the first conductivity type well so as to form source regions; and a step of burying a first insulation material on the first and second silicon films in each of the first trenches.
Claim 3
Dependent Claim
185 words
The manufacturing process of a semiconductor memory device according to claim 1, further comprising: a step of forming a second trench in each of portions of the first insulation materials and portions of a first conductivity well by etching down to a depth between bottoms of the source regions and bottoms of the first conductivity type well so as to form silicon columns; a step of burying a second insulation material in each of the second trenches, and etching back the first and second insulation materials down to a depth of an upper surface of the source region; a step of forming a gate insulating film on exposed side surfaces of each of the silicon columns, burying a first conductive film in each of the second trenches and spaces between silicon columns, and etching back the first conductive film so as to leave a gate electrode surrounding each silicon column, and burying a third insulation material in the second trenches; and a step of forming a drain region in each top of silicon columns and connecting a bit line to each of the drain regions.
Claim 4
Dependent Claim
54 words
The manufacturing process of a semiconductor memory device according to claim 2, comprising: a step of disposing a bit line contact deviated towards a corresponding bit line layer by a fraction of a distance between opposite faces of adjacent bit lines, and arranged at said fraction of distance from the end of drain region.
Claim 5
Dependent Claim
206 words
The manufacturing process of a semiconductor memory device according to claim 1, further comprising: a step of forming a second trench in each of the first insulation materials and portions of a first conductivity well by etching down to a depth between bottoms of the source regions and bottoms of the first conductivity type well so as to form silicon columns, while leaving the portions of first insulation materials between the second trenches substantially up to the height of a surface of the first conductivity type well; a step of burying a second insulation material in each of the second trenches, and etching back the second insulation materials down to a depth of an upper surface of the source region; a step of forming a gate insulating film on exposed side surfaces of each of the silicon columns, burying a second conductive film in each of the second trenches, and etching back the second conductive film so as to leave a gate electrode on a side wall of each silicon column, and burying a third insulation material in the second trenches; and a step of forming a drain region in each top of silicon columns and connecting a bit line to each of the drain regions.
Claim 6
Dependent Claim
54 words
The manufacturing process of a semiconductor memory device according to claim 4, comprising: a step of disposing a bit line contact deviated towards a corresponding bit line layer by a fraction of a distance between opposite faces of adjacent bit lines, and arranged at said fraction of distance from the end of drain region.
Claim 7
Dependent Claim
227 words
A manufacturing process of a semiconductor memory device, comprising; a step of forming a plurality of first trenches in a checkered configuration in a substrate, each of said first trenches having an opening; a step of forming an insulating film on a side wall of each first trench and forming a second trench having a smaller opening than that of the first trench deeper under from a bottom of each first trench; a step of introducing a first conductivity type impurity from a surface of the substrate so as to form a first conductivity type well in an upper portion of the substrate; a step of forming a capacitor insulating film on a side wall of each of second trenches, burying a first conductive film in each of second trenches so as to form a storage electrode, etching back the first conductive film in each of second trenches so as to expose a portion of the capacitor insulating film, and removing a part of the portion of the capacitor insulating film; a step of burying a silicon film doped with a second conductivity type impurity in each of the second trenches and introducing second conductivity type impurities to the first conductivity well so as to form source regions; and a step of burying a first insulation material in each of the first trenches on the silicon film.
Claim 8
Dependent Claim
227 words
A manufacturing process of a semiconductor memory device, comprising; a step of forming a plurality of first trenches in a checkered configuration in a substrate, each of said first trenches having an opening; a step of forming an insulating film on a side wall of each first trench and forming a second trench having a smaller opening than that of the first trench deeper under from a bottom of each first trench; a step of introducing a first conductivity type impurity from a surface of the substrate so as to form a first conductivity type well in an upper portion of the substrate; a step of forming a capacitor insulating film on a side wall of each of second trenches, burying a first conductive film in each of second trenches so as to form a storage electrode, etching back the first conductive film in each of second trenches so as to expose a portion of the capacitor insulating film, and removing a part of the portion of the capacitor insulating film; a step of burying a silicon film doped with a second conductivity type impurity in each of the second trenches and introducing second conductivity type impurities to the first conductivity well so as to form source regions; and a step of burying a first insulation material in each of the first trenches on the silicon film.
Claim 9
Dependent Claim
100 words
The manufacturing process of a semiconductor memory device according to claim 6, further comprising: a step of forming a gate insulating film on exposed side surfaces of each of the first trenches, burying a second conductive film in each of the first trenches, and etching back the second conductive film so as to leave a gate electrode on a side wall of each first trench, and burying a second insulation material in the first trenches; and a step of forming a drain region in each top of the substrate and connecting a bit line to each of the drain regions.
Claim 10
Dependent Claim
54 words
The manufacturing process of a semiconductor memory device according to claim 7, including: a step of disposing a bit line contact deviated towards a corresponding bit line layer by a fraction of a distance between opposite faces of adjacent bit lines, and arranged at said fraction of distance from the and of drain region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-18 | 2001-11-17 | 2002-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-18 | 2005-11-17 | 2006-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-18 | 2009-11-17 | 2010-05-19 | $7700.00 | Window Closed / Lapsed |