US5470778A — Method of manufacturing a semiconductor device

Claim 1

Independent Claim 94 words

A method for manufacturing a semiconductor device, which comprises the steps of: forming a first depression within an uppermost surface of a semiconductor device; forming a second depression continuous with the first depression and to be deeper than the first depression; burying a conductor in the first and second depressions to a level which is lower than the uppermost surface of the semiconductor substrate surface; and forming an insulating film on top of the conductor such that said insulating film abuts said conductor at a level below said uppermost surface of said semiconductor device.

Claim 2

Independent Claim 94 words

A method for manufacturing a semiconductor device, which comprises the steps of: forming a first depression within an uppermost surface of a semiconductor device; forming a second depression continuous with the first depression and to be deeper than the first depression; burying a conductor in the first and second depressions to a level which is lower than the uppermost surface of the semiconductor substrate surface; and forming an insulating film on top of the conductor such that said insulating film abuts said conductor at a level below said uppermost surface of said semiconductor device.

Claim 3

Dependent Claim 27 words

The method of claim 1 wherein said semiconductor substrate comprises a silicon substrate and said step of forming said insulating film comprises forming a silicon dioxide film.

Claim 4

Dependent Claim 53 words

The method of claim 1 and further comprising the steps of: forming a first doped region in said semiconductor substrate adjacent said second depression; forming a second doped region in said semiconductor substrate and spaced from said first doped region by a channel region; and forming a conductive region overlying said channel region.

Claim 5

Dependent Claim 41 words

The method of claim 1 wherein said step of forming a second depression further comprises forming a third depression within said uppermost surface, said first depression continuous with said first depression and spaced from said second depression by said first depression.

Claim 6

Dependent Claim 26 words

The method of claim 1 and further comprising forming an insulating layer within said first and second depressions prior to said step of burying a conductor.

Claim 7

Dependent Claim 21 words

The method of claim 1 wherein step of forming a second depression comprises forming said second depression through said first depression.

Claim 8

Dependent Claim 25 words

The method of claim 1 wherein the portion of said conductor within said first depression abuts the portion of said conductor within said second depression.

Claim 9

Independent Claim 156 words

A method of forming a memory cell within a semiconductor layer which includes a top surface, said method comprising the steps of: forming a first depression in said semiconductor layer such that said first depression is disposed within said semiconductor layer below said top surface; forming a second depression continuous to said first depression within said semiconductor layer, said second depression formed deeper than said first depression; forming a first doped region in said semiconductor layer adjacent said second depression; forming an insulating layer within said first and second depressions; forming a conductor adjacent said insulating layer within said first and second depressions; forming an insulating film on top of said conductor at an interface wherein said interface is formed inside said first depression below said top surface; forming a second doped region in said semiconductor layer and spaced from said first doped region by a channel region; and forming a gate over said channel region.

Claim 10

Independent Claim 156 words

A method of forming a memory cell within a semiconductor layer which includes a top surface, said method comprising the steps of: forming a first depression in said semiconductor layer such that said first depression is disposed within said semiconductor layer below said top surface; forming a second depression continuous to said first depression within said semiconductor layer, said second depression formed deeper than said first depression; forming a first doped region in said semiconductor layer adjacent said second depression; forming an insulating layer within said first and second depressions; forming a conductor adjacent said insulating layer within said first and second depressions; forming an insulating film on top of said conductor at an interface wherein said interface is formed inside said first depression below said top surface; forming a second doped region in said semiconductor layer and spaced from said first doped region by a channel region; and forming a gate over said channel region.

Claim 11

Dependent Claim 19 words

The method of claim 8 wherein said steps of forming first and second doped regions comprise forming n-doped regions.

Claim 12

Dependent Claim 16 words

The method of claim 8 wherein said first doped region is formed within said semiconductor layer.

Claim 13

Dependent Claim 32 words

The method of claim 8 wherein said step of forming a first doped region comprises forming a polysilicon region within said second depression and insulated from said conductor by said insulating layer.

Claim 14

Independent Claim 125 words

A method of forming a semiconductor device within a semiconductor layer which includes a top surface, said method comprising the steps of: forming a first depression in said semiconductor layer and extending below said top surface; forming a second depression in said semiconductor layer and linked to said first depression, said second depression formed deeper than said first depression; forming a first conductor within said second depression thereby creating a third depression within said second depression; forming a second conductor within said first and third depressions, said second conductor insulated from said first conductor; and forming an insulating film on top of said second conductor at an interface wherein the interface between the insulating film and the second conductor is formed inside the first depression.

Claim 15

Independent Claim 125 words

A method of forming a semiconductor device within a semiconductor layer which includes a top surface, said method comprising the steps of: forming a first depression in said semiconductor layer and extending below said top surface; forming a second depression in said semiconductor layer and linked to said first depression, said second depression formed deeper than said first depression; forming a first conductor within said second depression thereby creating a third depression within said second depression; forming a second conductor within said first and third depressions, said second conductor insulated from said first conductor; and forming an insulating film on top of said second conductor at an interface wherein the interface between the insulating film and the second conductor is formed inside the first depression.

Claim 16

Dependent Claim 53 words

The method of claim 12 and further comprising the steps of: forming a first doped region in said semiconductor layer and abutting said first conductor; forming a second doped region in said semiconductor layer and spaced from said first doped region by a channel region; and forming a gate over said channel region.

Claim 17

Independent Claim 190 words

A method of forming a memory cell within a semiconductor layer which includes an uppermost surface, said method comprising the steps of: forming a shallow depression within said semiconductor layer, said shallow depression having a sidewall; etching a portion of said semiconductor layer adjacent said shallow depression sidewall thereby forming a deep trench which overlaps said shallow depression, said deep trench extending further within said semiconductor layer than said shallow depression; forming a first conductive layer along a sidewall within said deep trench; forming a dielectric layer over said first conductive layer within said deep trench; forming a second conductive layer within said shallow depression and said deep trench, said second conductive layer having an uppermost surface disposed below said uppermost surface of said semiconductor layer; forming an insulating layer over said second conductive layer; forming a gate overlying a channel region within said semiconductor layer and spaced from said deep trench; and forming a first and second doped regions within said semiconductor layer adjacent said gate, said first doped region formed adjacent said deep trench and said second doped region spaced from said doped region by said channel region.

Claim 18

Independent Claim 190 words

A method of forming a memory cell within a semiconductor layer which includes an uppermost surface, said method comprising the steps of: forming a shallow depression within said semiconductor layer, said shallow depression having a sidewall; etching a portion of said semiconductor layer adjacent said shallow depression sidewall thereby forming a deep trench which overlaps said shallow depression, said deep trench extending further within said semiconductor layer than said shallow depression; forming a first conductive layer along a sidewall within said deep trench; forming a dielectric layer over said first conductive layer within said deep trench; forming a second conductive layer within said shallow depression and said deep trench, said second conductive layer having an uppermost surface disposed below said uppermost surface of said semiconductor layer; forming an insulating layer over said second conductive layer; forming a gate overlying a channel region within said semiconductor layer and spaced from said deep trench; and forming a first and second doped regions within said semiconductor layer adjacent said gate, said first doped region formed adjacent said deep trench and said second doped region spaced from said doped region by said channel region.

Claim 19

Dependent Claim 29 words

The method of claim 14 wherein: said shallow depression is between about 3000 and 6000 Å deep; and said deep trench is between about 3 and 5 μm deep.

Claim 20

Dependent Claim 17 words

The method of claim 14 wherein said shallow depression is formed by a reactive ion etching process.

Claim 21

Dependent Claim 25 words

The method of claim 14 wherein said step of forming a second conductive layer within said shallow depression and said deep trench comprises depositing polysilicon.

Claim 22

Dependent Claim 70 words

The method of claim 17 wherein said step of forming a second conductive layer within said shallow depression and said deep trench comprises the steps of: depositing a polysilicon layer over said uppermost surface of said semiconductor layer outside said shallow depression and said deep trench; and etching back said polysilicon layer such that said polysilicon layer has an uppermost surface disposed below said uppermost surface of said semiconductor layer.

Claim 23

Dependent Claim 35 words

The method of claim 14 wherein said step of forming an insulating layer over said conductive region comprises the steps of forming an oxide layer followed by forming a nitride layer over said oxide layer.

Claim 24

Dependent Claim 42 words

The method of claim 14 wherein said etching step further comprises forming a second deep trench which overlaps said shallow depression and is spaced from said deep trench, said second deep trench extending further within said semiconductor layer than said shallow depression.

Claim 25

Dependent Claim 24 words

The method of claim 14 wherein said step of forming a conductive layer along a sidewall within said deep trench comprises doping said sidewall.

Claim 26

Dependent Claim 38 words

The method of claim 14 wherein said step of forming a conductive layer along a sidewall within said deep trench comprises forming an insulating layer along said sidewall followed by forming a conductive layer along said insulating layer.

Claim 27

Independent Claim 164 words

A method of making a semiconductor storage device comprising the steps of: forming a first groove in a semiconductor substrate of one conductive type; forming a second groove deeper than the first groove, said second groove being stacked within said first groove; forming an insulating film within said second groove, said insulating film provided so as to expose a portion of said substrate; forming an accumulating electrode along the walls of said second groove wherein said accumulating electrode is brought into contact with the substrate at said portion which was exposed; adding impurities of the conductive type opposite that of the substrate to the substrate in said exposed section; burying an electrode in said first and second grooves wherein said electrode and said accumulating electrode are separated by a capacitor insulating film; and providing a MOS transistor within said substrate wherein, said MOS transistor includes first and second source/drain regions of said opposite conductive type, wherein said first source/drain region contacts said accumulating electrode.

Claim 28

Independent Claim 164 words

A method of making a semiconductor storage device comprising the steps of: forming a first groove in a semiconductor substrate of one conductive type; forming a second groove deeper than the first groove, said second groove being stacked within said first groove; forming an insulating film within said second groove, said insulating film provided so as to expose a portion of said substrate; forming an accumulating electrode along the walls of said second groove wherein said accumulating electrode is brought into contact with the substrate at said portion which was exposed; adding impurities of the conductive type opposite that of the substrate to the substrate in said exposed section; burying an electrode in said first and second grooves wherein said electrode and said accumulating electrode are separated by a capacitor insulating film; and providing a MOS transistor within said substrate wherein, said MOS transistor includes first and second source/drain regions of said opposite conductive type, wherein said first source/drain region contacts said accumulating electrode.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1998-11-27	1999-05-29	1999-11-28	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2002-11-27	2003-05-29	2003-11-28	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2006-11-27	2007-05-29	2007-11-28	$7700.00	Window Closed / Lapsed

Method of manufacturing a semiconductor device

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