Dynamic programming of bus master channels by intelligent peripheral devices using communication packets

Claim 3

The apparatus of claim 1, wherein the packets include a starting address packet of the address type, the starting address packet including the read/write bit.

Claim 4

The apparatus of claim 2, wherein the starting address packet contains an address that is DWord-aligned.

Claim 5

The apparatus of claim 2, wherein the packets further comprise another packet of either the control type or the data type.

Claim 6

The apparatus of claim 2, wherein the packets further comprise a second address packet of the address type, such that addressing information contained within the starting address packet and the second address packet is decoded as a single memory address.

Claim 7

The apparatus of claim 1, wherein the step of establishing comprises the step of arbitrating between the peripheral devices.

Claim 8

The apparatus of claim 1, wherein during a read operation, the step of performing the memory operation comprises the step of using the controller to transmit a second plurality of packets from the controller to the peripheral devices, each of the second plurality of packets being one of the plurality of packet types, such that the current bus master decodes the second plurality of packets.

Claim 9

The apparatus of claim 1, wherein each of the peripheral devices has an identification code comprising a plurality of ID bits, wherein the identification code is included as part of one of the packets, such that the controller identifies the peripheral device initiating the memory operation based on the identification codes.

Claim 10

The apparatus of claim 8, wherein the identification codes of the peripheral devices are assigned contiguously from a 2 n boundary, where n is an integer, such that the controller can assign a channel to a peripheral device initiating the memory operation using less than all of the ID bits of each of the identification codes.

Claim 11

A direct memory access (DMA) channel for enabling a peripheral device to dynamically program a memory access operation upon a memory, the channel comprising: a control circuit coupled to the memory, the control circuit receiving from the peripheral device a plurality of packets for performing the memory access operation, wherein the memory access operation is either a read operation or a write operation, the plurality of packets including a starting address packet and a subsequent packet, wherein the subsequent packet can be either a data packet data or a control packet, each of the plurality of packets including a plurality of packet type bits for identifying each of the packets as an address packet, a data packet, or a control packet, one of said plurality of packets including a read/write bit for identifying the memory access operation as either a read operation or a write operation, the control circuit recognizing the packets as address packets, data packets, or control packets based on the packet type bits, the control circuit controlling the memory access operation based on the starting address packet and the subsequent packet; and a storage device having a first input coupled to receive data read from the memory if the memory access operation is a read operation and a second input coupled to receive the packets received from the peripheral devices, the control circuit enabling either the first input or the second input based on the read/write bit, the storage device coupled to output the packets to the control circuit and to output the data read from the memory to the peripheral devices.

Claim 12

A direct memory access (DMA) channel for enabling a peripheral device to dynamically program a memory access operation upon a memory, the channel comprising: a control circuit coupled to the memory, the control circuit receiving from the peripheral device a plurality of packets for performing the memory access operation, wherein the memory access operation is either a read operation or a write operation, the plurality of packets including a starting address packet and a subsequent packet, wherein the subsequent packet can be either a data packet data or a control packet, each of the plurality of packets including a plurality of packet type bits for identifying each of the packets as an address packet, a data packet, or a control packet, one of said plurality of packets including a read/write bit for identifying the memory access operation as either a read operation or a write operation, the control circuit recognizing the packets as address packets, data packets, or control packets based on the packet type bits, the control circuit controlling the memory access operation based on the starting address packet and the subsequent packet; and a storage device having a first input coupled to receive data read from the memory if the memory access operation is a read operation and a second input coupled to receive the packets received from the peripheral devices, the control circuit enabling either the first input or the second input based on the read/write bit, the storage device coupled to output the packets to the control circuit and to output the data read from the memory to the peripheral devices.

Claim 13

The DMA channel of claim 10, wherein the storage device comprises a first in-first out memory.

Claim 14

The DMA channel of claim 11, wherein the packets are transmitted from the peripheral device serially.

Claim 15

The DMA channel of claim 12, wherein the plurality of packets further comprise a second address packet, wherein the first address packet and the second address packet are decoded as one memory address.

Claim 16

The DMA channel of claim 10, wherein the address packet contains an address that is DWord-aligned.

Claim 17

The apparatus of claim 14, wherein the starting address packet contains an upper thirty (30) bits of a thirty-two (32) bit address.

Claim 18

The DMA channel of claim 10, wherein the packets are transmitted and received isochronously.

Claim 19

The DMA channel of claim 10, wherein the packets are transmitted and received asynchronously.

Claim 20

A controller for enabling a plurality of peripheral devices to dynamically program read and write operations upon a memory, the controller comprising: a router coupled to receive from and transmit to the peripheral devices a plurality of packets of digital information for performing a plurality of memory operations, the plurality of packets including address packets, data packets, and control packets, each of the packets including a plurality of packet type bits for identifying each of the packets as either an address packet, a data packet, or a control packet, wherein each of the peripheral devices can initiate one of the memory operations by transmitting to the controller one of the address packets and a subsequent packet, wherein the subsequent packet is one of either the control packets or the data packets, wherein the address packet or the subsequent packet includes a read/write bit identifying the operation as a read operation or a write operation; and a channel coupled to the router and to the memory, the channel including: a data buffer coupled to the memory, the data buffer storing data read from or to be written to the memory, the data buffer inputting data that is to be written to the memory and contained within the packets if the packet type bits of said packets indicate that said packets are data packets; a control circuit coupled to the memory, the control circuit inputting information contained within the packets if the packet type bits of said packets indicate that said packets are address packets or control packets, the control unit recognizing the information within the address packets and the control packets as address information or control information, the control circuit controlling the read and write operations based on the address information and the control information; a second buffer coupled to receive the packets from the router; a third buffer coupled to provide to the router data read from the memory; a multiplexor having a first input coupled to receive data read from the memory from the data buffer and a second input coupled to receive the packets from the second buffer, the control circuit selecting either the first input or the second input based on the read/write bit; and a first in-first out (FIFO) memory storing the packets and the data read from the memory, the FIFO memory having an input coupled to an output of the multiplexor and having an output coupled to provide the packets to the data buffer and to the control circuit, the output further coupled to provide data read from the memory to the third buffer.

Claim 21

A controller for enabling a plurality of peripheral devices to dynamically program read and write operations upon a memory, the controller comprising: a router coupled to receive from and transmit to the peripheral devices a plurality of packets of digital information for performing a plurality of memory operations, the plurality of packets including address packets, data packets, and control packets, each of the packets including a plurality of packet type bits for identifying each of the packets as either an address packet, a data packet, or a control packet, wherein each of the peripheral devices can initiate one of the memory operations by transmitting to the controller one of the address packets and a subsequent packet, wherein the subsequent packet is one of either the control packets or the data packets, wherein the address packet or the subsequent packet includes a read/write bit identifying the operation as a read operation or a write operation; and a channel coupled to the router and to the memory, the channel including: a data buffer coupled to the memory, the data buffer storing data read from or to be written to the memory, the data buffer inputting data that is to be written to the memory and contained within the packets if the packet type bits of said packets indicate that said packets are data packets; a control circuit coupled to the memory, the control circuit inputting information contained within the packets if the packet type bits of said packets indicate that said packets are address packets or control packets, the control unit recognizing the information within the address packets and the control packets as address information or control information, the control circuit controlling the read and write operations based on the address information and the control information; a second buffer coupled to receive the packets from the router; a third buffer coupled to provide to the router data read from the memory; a multiplexor having a first input coupled to receive data read from the memory from the data buffer and a second input coupled to receive the packets from the second buffer, the control circuit selecting either the first input or the second input based on the read/write bit; and a first in-first out (FIFO) memory storing the packets and the data read from the memory, the FIFO memory having an input coupled to an output of the multiplexor and having an output coupled to provide the packets to the data buffer and to the control circuit, the output further coupled to provide data read from the memory to the third buffer.

Claim 22

The controller of claim 18, wherein the digital information is isochronous.

Claim 23

The controller of claim 18, wherein the digital information is asynchronous.

Claim 24

A computer system comprising: a processor; a memory coupled to the processor; a plurality of peripheral devices coupled to the processor; and a controller coupled to the peripheral devices and to the memory the controller including: a control circuit coupled to receive a plurality of packets transmitted from one of the peripheral devices, the packets for performing a memory access operation upon the memory, wherein the memory access operation is either a read operation or a write operation, each of the plurality of packets including a plurality of packet type bits for identifying each of the packets as an address packet, a data packet, or a control packet, one of said plurality of packets including a read/write bit for identifying the memory access operation as either a read operation or a write operation, the control circuit controlling the memory access operation based on the packet type bits and the read /write bit; and a storage device coupled to the control circuit, the storage device receiving the packets from said one of the peripheral devices, the storage circuit outputting address packets and control packets to the control circuit, the storage circuit outputting data contained in the data packets to the memory if the read/write bit indicates that the memory access operation is a write operation, the storage device receiving data read from the memory and outputting the data read from the memory to the peripheral devices if the memory access operation is a read operation.

Claim 25

A computer system comprising: a processor; a memory coupled to the processor; a plurality of peripheral devices coupled to the processor; and a controller coupled to the peripheral devices and to the memory the controller including: a control circuit coupled to receive a plurality of packets transmitted from one of the peripheral devices, the packets for performing a memory access operation upon the memory, wherein the memory access operation is either a read operation or a write operation, each of the plurality of packets including a plurality of packet type bits for identifying each of the packets as an address packet, a data packet, or a control packet, one of said plurality of packets including a read/write bit for identifying the memory access operation as either a read operation or a write operation, the control circuit controlling the memory access operation based on the packet type bits and the read /write bit; and a storage device coupled to the control circuit, the storage device receiving the packets from said one of the peripheral devices, the storage circuit outputting address packets and control packets to the control circuit, the storage circuit outputting data contained in the data packets to the memory if the read/write bit indicates that the memory access operation is a write operation, the storage device receiving data read from the memory and outputting the data read from the memory to the peripheral devices if the memory access operation is a read operation.

Claim 26

The computer system of claim 21, wherein the plurality of packets including a starting address packet and a subsequent packet, wherein the subsequent packet can be either a data packet data or a control packet, wherein the control circuit further controls the memory access operation based on the starting address packet and the subsequent packet.

Claim 27

The computer system of claim 21, wherein the storage device comprises a first in-first out (FIFO) memory.

Claim 28

The computer system of claim 21, wherein the storage device further comprises a multiplexor having an output coupled to the FIFO memory and having a plurality of inputs, wherein the inputs are enabled or disabled by the control circuit based on the read/write bit.

Claim 29

The computer system of claim 21, further comprising a high-speed serial bus coupling the peripheral devices to the controller, such that the packets are transmitted from the peripheral device to the controller on the high-speed serial bus.

Claim 30

The computer system of claim 21, wherein the packets are communicated asynchronously.

Claim 31

The computer system of claim 21, wherein the packets are communicated isochronously.

Claim 34

The method of claim 28, wherein the packets comprise a first packet of the address type.

Claim 35

The method of claim 29, wherein the first packet includes the read/write bit.

Claim 36

The method of claim 29, wherein the packets further comprise a second packet of the address type, such that the address information contained within the first packet and the address information contained within the second packet are decoded into a single memory address.

Claim 37

The method of claim 29, wherein the packets further comprise a subsequent packet of either the control type or the data type.

Claim 38

The method of claim 28, wherein the step of establishing comprises the step of arbitrating between the peripheral devices.

Claim 39

The method of claim 28, wherein the step of performing the memory operation comprises the step of using the controller to transmit a second plurality of packets from the controller to the peripheral devices, wherein the current bus master decodes the second plurality of packet.

Claim 40

The method of claim 28, wherein, in the initiating step, the packets are communicated asynchronously.

Claim 41

The method of claim 28, wherein, in the initiating step, the packets are communicated isochronously.

Claim 44

The apparatus of claim 37, wherein the packets include a starting address packet of the address type and a subsequent address packet of the data type or the control type, the starting address packet including the read/write bit.

Claim 45

The apparatus of claim 37, wherein the starting address packet contains an address that is DWord-aligned.

Claim 46

The apparatus of claim 37, wherein the packets further comprise a second address packet of the address type, such that addressing information contained within the starting address packet and the second address packet is decoded as a single memory address.

Claim 47

The apparatus of claim 37, wherein each of the peripheral devices has an identification code comprising a plurality of ID bits, wherein the identification code is included as part of one of the packets, such that the controller identifies the peripheral device initiating the memory operation based on the identification codes.

Claim 50

The device of claim 42, wherein the plurality of packets are transmitted from said one of the peripheral devices on a high-speed serial bus.

Claim 51

The device of claim 43, wherein the packets are transmitted and received asynchronously.

Claim 52

The device of claim 43, wherein the packets are transmitted and received isochronously.

Claim 53

In a controller coupled to a plurality of peripheral devices by a bus and coupled to a memory, the controller including a plurality of direct memory access (DMA) channels, a method of enabling any of the plurality of peripheral devices to dynamically program read and write operations upon the memory, the method comprising the steps of: receiving from one of the plurality of peripheral devices a plurality of packets of information for performing a memory operation, each of the packets being one of a plurality of packet types, the plurality of packet types including an address type, a data type, and a control type, each of the packets including a plurality of packet type bits for identifying each packet as an address type, a data type, or a control type, wherein the plurality of packets received from the current bus master include a starting address packet and a subsequent packet, wherein the subsequent packet can be of either the data type or the control type, one of the plurality of packets including a read/write bit identifying the operation as a read operation or a write operation, at least one of the plurality of packets having a device identifier for identifying said one of the peripheral devices; selecting one of the plurality of DMA channels based on the device identifier; forwarding the plurality of packets to the selected DMA channel; identifying the memory operation as either a read operation or a write operation based on the read/write bit; identifying the packet types of the plurality of packets based on said at least one packet type bit; and performing the memory operation based on a content of the starting address packet and the subsequent packet.

Claim 54

In a controller coupled to a plurality of peripheral devices by a bus and coupled to a memory, the controller including a plurality of direct memory access (DMA) channels, a method of enabling any of the plurality of peripheral devices to dynamically program read and write operations upon the memory, the method comprising the steps of: receiving from one of the plurality of peripheral devices a plurality of packets of information for performing a memory operation, each of the packets being one of a plurality of packet types, the plurality of packet types including an address type, a data type, and a control type, each of the packets including a plurality of packet type bits for identifying each packet as an address type, a data type, or a control type, wherein the plurality of packets received from the current bus master include a starting address packet and a subsequent packet, wherein the subsequent packet can be of either the data type or the control type, one of the plurality of packets including a read/write bit identifying the operation as a read operation or a write operation, at least one of the plurality of packets having a device identifier for identifying said one of the peripheral devices; selecting one of the plurality of DMA channels based on the device identifier; forwarding the plurality of packets to the selected DMA channel; identifying the memory operation as either a read operation or a write operation based on the read/write bit; identifying the packet types of the plurality of packets based on said at least one packet type bit; and performing the memory operation based on a content of the starting address packet and the subsequent packet.

Claim 55

The method of claim 46, wherein the plurality of packets comprise a second packet of the address type, such that the address information contained within the starting address packet and the address information contained within the second packet are decoded into a single memory address.

Claim 56

The method of claim 46, wherein the receiving step comprises the step of receiving asynchronously transmitted packets.

Claim 57

The method of claim 46, wherein the receiving step comprises the step of receiving isochronously transmitted packets.