Mesh parallel computer architecture apparatus and associated methods

Claim 2

Digital data processing apparatus for synchronously processing data from a host computer, comprising: program memory means for storing data, and bus means connecting said program memory means to the host computer; a master processor element and an array of slave processor elements, said master processor element having means to access said data within said program memory and for broadcasting instructions to said array; and input/output module means connected to communicate with said bus means and having a plurality of data links connected to said array, each of said data links providing serial communication with selected slave processor elements; wherein each of said slave processor elements comprises (i) an input/output processor section having interprocessor communication links for communicating data to and from selected other processor elements within said array, and further having means for communicating data to and from said input/output module means, (ii) internal memory means having a storage capacity of at least 128 kilobytes for storing executable code, and (iii) a core processor section for processing said executable code and said instructions, each of said processor sections being operable independently from the other of said processor sections; said slave processor elements synchronously executing at least one of said instructions and said executable code at a throughput rate of at least 120 MFLOPS.

Claim 3

A monolithic processor element comprising: memory; an external port for receiving instructions; a core processor for processing instructions received through the external port; a set of selectable link ports; an input/output register set for holding data transferred between memory and the selectable link ports and transferred between selectable link ports; a bus system for transfer of data between the core processor and memory and between the input/output register set and memory; and an I/O controller which, for successive data elements, performs a direct memory access to read the data elements from memory to the input/output register set, and after a programmable number of cycles of data transfers between selectable ports through the input/output register set, performs a direct memory access to write the data elements from the input/output register set to memory.

Claim 4

A monolithic processor element comprising: memory; an external port for receiving instructions; a core processor for processing instructions received through the external port; a set of selectable link ports; an input/output register set for holding data transferred between memory and the selectable link ports and transferred between selectable link ports; a bus system for transfer of data between the core processor and memory and between the input/output register set and memory; and an I/O controller which, for successive data elements, performs a direct memory access to read the data elements from memory to the input/output register set, and after a programmable number of cycles of data transfers between selectable ports through the input/output register set, performs a direct memory access to write the data elements from the input/output register set to memory.

Claim 5

The monolithic processor of claim 2 wherein the I/O controller selects transmit and receive link ports and is programmed by a transfer control data structure which identifies memory addresses for the direct memory accesses, selects transmit and receive link ports and identifies the programmable number of cycles of data transfers.

Claim 6

The monolithic processor of claim 3 wherein the transfer control data structure comprises transmit and receive subarray parameters defining a two dimensional subarray and by which the I/O controller determines addresses from which data elements are read and addresses into which data elements are written.

Claim 7

The monolithic processor of claim 3 wherein the transfer data control structure comprises a chain pointer for pointing to subsequent transfer control data structures for automatic reprogramming of the I/O controller and continued data transfer.

Claim 8

The monolithic processor of claim 2 wherein the I/O controller is programmable to write data into memory from the input/output register set in each of said programmable number of cycles in a broadcast communication mode.

Claim 9

The monolithic processor of claim 2 wherein said processor element has a throughput rate of at least 120 MFLOPS.

Claim 10

The monolithic processor of claim 2 further comprising means for processing data as either SIMD or MIMD compatible data.

Claim 11

The monolithic processor of claim 2 further comprising a set of six link ports for communicating on a nearest-neighbor mesh with adjacent processors, each of said link ports providing a multiple bit wide data path.

Claim 12

The monolithic processor of claim 9 wherein four link ports provide nearest-neighbor mesh communication with four adjacent processors and two link ports provide fault tolerance with two of said four adjacent processors in the event of a failure.

Claim 13

A digital data processing apparatus for synchronously processing data from a host computer, comprising: a program memory for storing data; a bus connecting the program memory to the host computer; a master processor element and an array of slave processor elements, the master processor element having means to access said data within said program memory and for broadcasting instructions to said array; and an input/output module connected to communicate with the bus and having a plurality of data links connected to the array, each of the data links providing serial communication with selected slave processor elements; wherein each of the slave processor elements comprises (i) slave memory and an external port for receiving instructions; (ii) a core processor for processing instructions received through the external port; (iii) a set of selectable link ports; (iv) an input/output register set for holding data transferred between slave memory and the selectable link ports and transferred between selectable link ports; (v) a bus system for transfer of data between the core processor and slave memory, and between the input/output register set and slave memory; and (vi) an I/O controller which, for successive data elements, performs a direct memory access to read the data elements from slave memory to the input/output register set, and after a programmable number of cycles of data transfers between selectable ports through the input/output register set, performs a direct memory access to write the data elements from the input/output register set to slave memory.

Claim 14

A digital data processing apparatus for synchronously processing data from a host computer, comprising: a program memory for storing data; a bus connecting the program memory to the host computer; a master processor element and an array of slave processor elements, the master processor element having means to access said data within said program memory and for broadcasting instructions to said array; and an input/output module connected to communicate with the bus and having a plurality of data links connected to the array, each of the data links providing serial communication with selected slave processor elements; wherein each of the slave processor elements comprises (i) slave memory and an external port for receiving instructions; (ii) a core processor for processing instructions received through the external port; (iii) a set of selectable link ports; (iv) an input/output register set for holding data transferred between slave memory and the selectable link ports and transferred between selectable link ports; (v) a bus system for transfer of data between the core processor and slave memory, and between the input/output register set and slave memory; and (vi) an I/O controller which, for successive data elements, performs a direct memory access to read the data elements from slave memory to the input/output register set, and after a programmable number of cycles of data transfers between selectable ports through the input/output register set, performs a direct memory access to write the data elements from the input/output register set to slave memory.

Claim 15

The apparatus of claim 11 wherein each I/O controller selects transmit and receive link ports and is programmed by a transfer control data structure which identifies memory addresses for the direct memory accesses, selects transmit and receive link ports and identifies the programmable number of cycles of data transfers.

Claim 16

The apparatus of claim 12 wherein the transfer control data structure comprises transmit and receive subarray parameters defining a two dimensional subarray and by which said I/O controller determines addresses from which data elements are read and addresses into which data elements are written.

Claim 17

The apparatus of claim 12 wherein the transfer data control structure comprises a chain pointer for pointing to subsequent transfer control data structures for automatic reprogramming of said I/O controller and continued data transfer.

Claim 18

The apparatus of claim 11 wherein each I/O controller is programmable to write data into slave memory from each input/output register set in each of said programmable number of cycles in a broadcast communication mode.

Claim 19

The apparatus of claim 11 further comprising a buffer for electronically buffering the instructions between the program memory and the array.

Claim 20

The apparatus of claim 11 wherein each slave processor element comprises means for processing data as either SIMD or MIMD compatible data.

Claim 21

The apparatus of claim 11 wherein said each slave processor element further comprises a set of six link ports for communicating on a nearest-neighbor mesh with adjacent processors, each of said link ports providing a multiple bit wide data path.

Claim 22

The apparatus of claim 18 wherein four link ports provide nearest-neighbor mesh communication with four adjacent processors and two link ports provide fault tolerance with two of said four adjacent processors in the event of a failure.