Patent US5158324A successfully refreshed from Google Patents.
Patent US5751656A successfully refreshed from Google Patents.
US5751656A
Expired / Lapsed
US
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Synchronous DRAM memory with asynchronous column decode
Assignee: Micron Technology Inc
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Filing: 1996-12-23
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Granted: 1998-05-12
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Expires: 2016-12-23
Abstract
Abstract Disclosed is a synchronous DRAM memory module with control circuitry that allows the memory module to operate partially asynchronously. Specifically, a circuit is disclosed which utilizes address transition detection to begin decoding the column-address immediately after a new column-address is present on the address bus lines and without waiting for the column-address strobe signal to synchronize with the rising or falling edge of the synchronizing clock signal. Also disclosed is a manner of controlling the latching circuitry whereby each new column-address may be decoded and held within a buffer until the column-address strobe signal notifies the circuitry that the column-address is correct and is to be input into the microprocessor. Thus, each new column-address will be decoded immediately after it is present on the address lines and undesired column-addresses will be discarded, while desired column-addresses are input into the memory array bank immediately upon the presence of the column-address strobe which denotes that the column-address is final. The present invention improves the access times of read and write operations in synchronous DRAM memory by up to a complete clock cycle.
Inventors
- 👤 Scott Schaefer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:30
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/408; G11C11/4082; G11C11/4087; G11C7/10; G11C7/1015; G11C7/1018; G11C7/1027; G11C7/1072; G11C8/00; G11C8/06; G11C8/10; G11C8/18
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
136 words
A method of addressing an array of memory cells which are arranged in rows and columns and which are addressed by a row-address and a column-address of a selected memory cell to be communicated with by a microprocessor, the row-address and the column-address becoming available to a row-address decoding circuit and column-address decoding circuit at separate times, the method comprising: generating an internal signal at predetermined repeating intervals; beginning one of a column-address decoding operation and a row-address decoding operation in synchronization with the internal signal, such that said one of the column-address decoding operation and the row-address decoding operation begins only a selected amount of time after a generation of the internal signal; and beginning the other of said one of a column-address decoding operation and a row-address decoding operation independently of the internal signal.
Claim 2
Independent Claim
136 words
A method of addressing an array of memory cells which are arranged in rows and columns and which are addressed by a row-address and a column-address of a selected memory cell to be communicated with by a microprocessor, the row-address and the column-address becoming available to a row-address decoding circuit and column-address decoding circuit at separate times, the method comprising: generating an internal signal at predetermined repeating intervals; beginning one of a column-address decoding operation and a row-address decoding operation in synchronization with the internal signal, such that said one of the column-address decoding operation and the row-address decoding operation begins only a selected amount of time after a generation of the internal signal; and beginning the other of said one of a column-address decoding operation and a row-address decoding operation independently of the internal signal.
Claim 3
Dependent Claim
20 words
A method as recited in claim 1, wherein the internal signal is a clock signal operating at a selected frequency.
Claim 4
Dependent Claim
39 words
A method as recited in claim 1, wherein the beginning of said one of the column-address decoding operation and the row-address decoding operation begins in response to a control signal issued only after the generation of the internal signal.
Claim 5
Dependent Claim
53 words
A method as recited in claim 1, wherein the internal signal is a clock signal operating at a selected frequency, and wherein the beginning of said one of the column-address decoding operation and the row-address decoding operation begins in response to a control signal issued only after the generation of the internal signal.
Claim 6
Dependent Claim
52 words
A method as recited in claim 4, wherein the signal occurring independently of the internal signal is a row-address strobe issued by a decoding circuit to indicate the presence of a stable row-address on an address bus that is in electrical communication with the row-address decoding circuit and the column-address decoding circuit.
Claim 7
Dependent Claim
69 words
A method as recited in claim 4, further comprising the issuance of a column-address strobe issued by a decoding circuit after a generation of the internal signal to indicate the presence of a stable column-address on an address bus that is in electrical communication with the row-address decoding circuit and the column-address decoding circuit, and wherein the column-addressing operation is started prior to the issuance of the column-address strobe.
Claim 8
Dependent Claim
38 words
A method of addressing an array of memory cells as recited in claim 1, wherein the row-address decoding operation begins in synchronization with the internal signal, and wherein the column-address decoding operation begins independently of the internal signal.
Claim 9
Dependent Claim
29 words
A method of addressing an array of memory cells as recited in claim 1, wherein the memory array comprises an array of synchronously dynamically refreshable random access memory cells.
Claim 10
Dependent Claim
45 words
A method of addressing an array of memory cells as recited in claim 1, further comprising conducting a plurality of sequential operations in burst mode in which contiguous groups of memory cells are addressed successively with a timing that is coordinated with the internal signal.
Claim 11
Dependent Claim
67 words
A method as recited in claim 7, wherein beginning the other of said one of the column-address decoding operation and the row-address decoding operation further comprises: setting a column-address latch to a transparent state such that each new column-address occurring on the address bus enters the column-address latch; and latching a column-address into the column-address latch upon sensing the occurrence of the column-address on the address bus.
Claim 12
Independent Claim
157 words
A method of addressing an array of memory cells which are arranged in rows and columns and which are addressed by a row-address and a column-address of a selected memory cell to be communicated with by a microprocessor, the row-address and column-address being present at separate times on an address bus, the method comprising: decoding a row-address in synchronization with an internal signal generated at predetermined repeating intervals; setting a column-address latch to a transparent state that each new column-address present on the address bus enters the column-address latch; latching a column-address into the column-address latch upon sensing the presence of the column-address on the address bus; decoding the column-address independently of the internal signal generated at the predetermined repeating intervals; and conducting a plurality of operations in burst mode in which contiguous groups of memory cells are addressed successively with a timing that is coordinated with a series of consecutive addresses in response the internal signal.
Claim 13
Independent Claim
157 words
A method of addressing an array of memory cells which are arranged in rows and columns and which are addressed by a row-address and a column-address of a selected memory cell to be communicated with by a microprocessor, the row-address and column-address being present at separate times on an address bus, the method comprising: decoding a row-address in synchronization with an internal signal generated at predetermined repeating intervals; setting a column-address latch to a transparent state that each new column-address present on the address bus enters the column-address latch; latching a column-address into the column-address latch upon sensing the presence of the column-address on the address bus; decoding the column-address independently of the internal signal generated at the predetermined repeating intervals; and conducting a plurality of operations in burst mode in which contiguous groups of memory cells are addressed successively with a timing that is coordinated with a series of consecutive addresses in response the internal signal.
Claim 14
Dependent Claim
26 words
A method as recited in claim 11, wherein the presence of a the column-address on the address bus is sensed by an address transition detection circuit.
Claim 15
Dependent Claim
20 words
A method as recited in claim 11, wherein the internal signal is a clock signal operating at a selected frequency.
Claim 16
Dependent Claim
27 words
A method as recited in claim 11, wherein decoding the row-address begins in response to a control signal issued only after the generation of the internal signal.
Claim 17
Dependent Claim
41 words
A method as recited in claim 11, wherein the internal signal is a clock signal operating at a selected frequency, and wherein decoding the row-address begins in response to a control signal issued only after the generation of the internal signal.
Claim 18
Dependent Claim
37 words
A method as recited in claim 15, wherein the signal occurring independently of the internal signal is a row-address strobe issued by a decoding circuit to indicate the presence of a stable row-address on the address bus.
Claim 19
Dependent Claim
54 words
A method as recited in claim 16, further comprising the issuance of a column-address strobe issued by the decoding circuit after a generation of the internal signal to indicate the presence of a stable column-address on the address bus, and wherein the column-addressing operation is started prior to the issuance of the column-address strobe.
Claim 20
Dependent Claim
29 words
A method of addressing an array of memory cells as recited in claim 11, wherein the memory array comprises an array of synchronously dynamically refreshable random access memory cells.
Claim 21
Independent Claim
209 words
A method of addressing an array of memory cells which are arranged in rows and columns and which are addressed by a row-address and a column-address of a selected memory cell to be communicated with by a microprocessor, the row-address and column-address being present at separate times on an address bus, the address bus being in electrical connection with a column-address latch and a row-address batch, the method comprising: generating an internal signal at predetermined repeating intervals; issuing a row-address on the address bus; setting the column-address latch to a transparent state, such that each column-address appearing on the address bus is entered into the column-address latch; beginning decoding of the row-address in synchronization with the internal signal; issuing a column-address on the address bus; detecting the presence of the column-address on the address bus with an address transition detection module; latching the column-address in the column-address latch in response to the detection of the presence of the column-address on the address bus; beginning decoding of the column-address upon latching the column-address latch and independently of the internal signal; and conducting a plurality of sequential operations in burst mode in which contiguous groups of memory cells are addressed successively with a timing that is coordinated with the internal signal.
Claim 22
Independent Claim
209 words
A method of addressing an array of memory cells which are arranged in rows and columns and which are addressed by a row-address and a column-address of a selected memory cell to be communicated with by a microprocessor, the row-address and column-address being present at separate times on an address bus, the address bus being in electrical connection with a column-address latch and a row-address batch, the method comprising: generating an internal signal at predetermined repeating intervals; issuing a row-address on the address bus; setting the column-address latch to a transparent state, such that each column-address appearing on the address bus is entered into the column-address latch; beginning decoding of the row-address in synchronization with the internal signal; issuing a column-address on the address bus; detecting the presence of the column-address on the address bus with an address transition detection module; latching the column-address in the column-address latch in response to the detection of the presence of the column-address on the address bus; beginning decoding of the column-address upon latching the column-address latch and independently of the internal signal; and conducting a plurality of sequential operations in burst mode in which contiguous groups of memory cells are addressed successively with a timing that is coordinated with the internal signal.
Claim 23
Dependent Claim
29 words
A method of addressing an array of memory cells as recited in claim 19, wherein the memory array comprises an array of synchronously dynamically refreshable random access memory cells.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-11 | 2001-11-10 | 2002-05-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-11 | 2005-11-10 | 2006-05-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-11 | 2009-11-10 | 2010-05-12 | $7700.00 | Window Closed / Lapsed |