US4719602A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory with improved column access
Assignee: POONJA MOHAMED AS TRUSTEE UNDER VISIC Inc LIQUIDATING TRUST AGREEMENT DATED DECEMBER 18 1990
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Filing: 1985-02-07
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Granted: 1988-01-12
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Expires: 2005-02-07
Abstract
Abstract A semiconductor memory device having an improved system for randomly accessing a preselected set of memory locations. The invention includes a set of "secondary sense amplifiers" which act as a high speed buffer between the memory's normal sense amplifiers and the memory's data input and output buffers. The secondary sense amplifiers are connected to selected ones of the sense amplifiers in accordance with a first predefined subset of the memory's column address signals. A decoder circuit, which is directly responsive to a second predefined subset of the column address signals, selects one of the secondary sense amplifiers and connects it to the memory's data input and output buffers. Since the decoder is directly responsive to the second predefined subset of the column address signals and does not need to latch in new address values after the detection of an address signal transition, all the secondary sense amplifiers can be accessed much faster than the other data storage locations in the memory.
Inventors
- 👤 Mohammed E. U. Hag
- 👤 Peter J. Bagnall
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:57
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1078; G11C7/1096; G11C7/06; G11C7/065; G11C7/1015; G11C7/103; G11C7/1033; G11C7/1051; G11C8/00; G11C8/10
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
155 words
In a semiconductor memory device having: a multiplicity of data storage locations arranged in rows and columns, said storage locations being addressed by a plurality of binary address signals; said address signals being divided into row address signals and column address signals; said column address signals being further divided into low and high order column address signals; a set of sense amplifiers for latching and transferring data to and from a selected row of said data storage locations; and data input and output buffers for receiving and transmitting data; the improvement comprising: a plurality of secondary sense amplifiers for latching and transferring data to and from selected ones of said sense amplifiers, said sense amplifiers being selected in accordance with said high order column address signals; and decoder means responsive to said low order column address signals for selecting one of said secondary sense amplifiers and connecting it to said data input and output buffers.
Claim 2
Dependent Claim
155 words
In a semiconductor memory device having: a multiplicity of data storage locations arranged in rows and columns, said storage locations being addressed by a plurality of binary address signals; said address signals being divided into row address signals and column address signals; said column address signals being further divided into low and high order column address signals; a set of sense amplifiers for latching and transferring data to and from a selected row of said data storage locations; and data input and output buffers for receiving and transmitting data; the improvement comprising: a plurality of secondary sense amplifiers for latching and transferring data to and from selected ones of said sense amplifiers, said sense amplifiers being selected in accordance with said high order column address signals; and decoder means responsive to said low order column address signals for selecting one of said secondary sense amplifiers and connecting it to said data input and output buffers.
Claim 3
Dependent Claim
92 words
A memory device as set forth in claim 1, wherein said memory device is a dynamic memory device; further including static column means comprising: address transition detection means for detecting a change in any of said said high order column address signals and for generating an address transition signal in response to any such change; and column decoder means, responsive to said address transition signal, for connecting said secondary sense amplifiers to selected ones of said sense amplifiers in accordance with the current signal values of said high order column address signals.
Claim 4
Dependent Claim
50 words
A memory device as set forth in claim 2, wherein said decoder means is responsive to said low order column address signals; and said column decoder means is responsive to changes in said high order column address signals only after said address transition detection means generates said address transition signal.
Claim 5
Dependent Claim
21 words
A memory device as set forth in claim 1, said low order column address signals including at least two address signals.
Claim 6
Dependent Claim
62 words
A memory device as set forth in claim 1, further including: write enable means, responsive to a write enable signal, for connecting said data input buffer to said decoder means, and thereby enabling the transfer of data from said input buffer through said decoder means into the secondary sense amplifier corresponding to the current value of said low order column address signals.
Claim 7
Dependent Claim
160 words
In a method of operating a dynamic memory device; said device having: a multiplicity of data storage locations arranged in rows and columns, said storage locations being addressed by a plurality of binary address signals; said address signals being divided into row address signals and column address signals; said column address signals being further divided into low and high order column address signals; a set of sense amplifiers for latching and transferring data to and from a selected row of said data storage locations; and data input and output buffers for receiving and transmitting data; the steps of: providing a plurality of secondary sense amplifiers; transferring data between said secondary sense amplifiers and selected ones of said sense amplifiers, said sense amplifiers being selected in accordance with said high order column address signals; and selecting one of said secondary sense amplifiers in accordance with said low order column address signals and connecting it to said data input and output buffers.
Claim 8
Dependent Claim
160 words
In a method of operating a dynamic memory device; said device having: a multiplicity of data storage locations arranged in rows and columns, said storage locations being addressed by a plurality of binary address signals; said address signals being divided into row address signals and column address signals; said column address signals being further divided into low and high order column address signals; a set of sense amplifiers for latching and transferring data to and from a selected row of said data storage locations; and data input and output buffers for receiving and transmitting data; the steps of: providing a plurality of secondary sense amplifiers; transferring data between said secondary sense amplifiers and selected ones of said sense amplifiers, said sense amplifiers being selected in accordance with said high order column address signals; and selecting one of said secondary sense amplifiers in accordance with said low order column address signals and connecting it to said data input and output buffers.
Claim 9
Dependent Claim
83 words
In the method of claim 6, the additional steps of: detecting a change in any of said said high order column address signals and generating an address transition signal in response to any such change; and in response to said address transition signal, connecting said secondary sense amplifiers to selected ones of said sense amplifiers in accordance with the current signal values of said high order column address signals; wherein said selecting step is directly responsive to said low order column address signals.
Claim 10
Dependent Claim
53 words
In the method of claim 7, the additional step of: in response to the receipt of a write enable signal, enabling the writing of data into said memory by selecting one of said secondary sense amplifiers in accordance with said low order column address signals and connecting it to said data input buffer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-11 | 1991-07-13 | 1992-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-11 | 1995-07-13 | 1996-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-11 | 1999-07-13 | 2000-01-12 | $7700.00 | Window Closed / Lapsed |