Data processing condition code flags

Claim 1

Apparatus for data processing, said apparatus comprising: (i) a plurality of registers for storing data words to be manipulated, each of said registers having at least an N-bit capacity; and (ii) an arithmetic logic unit having an N-bit datapath and responsive program instruction words to perform arithmetic logic operations specified by said program instruction words; wherein (iii) said arithmetic logic unit is responsive to at least one parallel operation program instruction word that separately performs a first arithmetic logic operation upon a first (N/2)-bit input operand data word and a second arithmetic logic operation upon a second (N/2)-bit input operand data word; and (iv) said arithmetic logic unit sets a first set of condition code flags in dependence upon said first arithmetic logic operation and sets a second set of condition code flags in dependence upon said second arithmetic logic operation, wherein said arithmetic logic unit is responsive to a conditional select instruction that moves one of a first (N/2)-bit input operand data word stored in a first source register and a first (N/2)-bit input operand data word stored in a second source register to a destination register of said plurality of registers in dependence upon said first set of condition flags and moves one of a second (N/2)-bit input operand data word stored in a first source register and a second (N/2)-bit input operand data word stored in a second source register to said destination register in dependence upon said second set of condition flags.

Claim 8

A method of processing data, said method comprising the steps of: (i) storing data words to be manipulated in a plurality of registers, each of said registers having at least an N-bit capacity; and (ii) in response to program instruction words, performing, with an arithmetic logic unit having an N-bit datapath, arithmetic logic operations specified by said program instruction words; wherein (iii) in response to at least one parallel operation program instruction word separately performing a first arithmetic logic operation upon a first (N/2)-bit input operand data word and a second arithmetic logic operation upon a second (N/2)-bit input operand data word; (iv) setting a first set of condition code flags in dependence upon said first arithmetic logic operation; and (v) setting a second set of condition code flags in dependence upon said second arithmetic logic operation wherein said arithmetic logic unit is responsive to a conditional select instruction that moves one of said first N/2)-bit input operand data words stored in a first source register and one of said first (N/2)-bit input operand data word stored in a second source register to a destination register of said plurality of registers in dependence upon said first set of condition flags and moves one of said second (N/2)-bit input operand data words stored in a first source register and one of said second (N/2)-bit input operand data words stored in a second source register to said destination register in dependence upon said second set of condition flags.

Claim 9

A method of processing data, said method comprising the steps of: (i) storing data words to be manipulated in a plurality of registers, each of said registers having at least an N-bit capacity; and (ii) in response to program instruction words, performing, with an arithmetic logic unit having an N-bit datapath, arithmetic logic operations specified by said program instruction words; wherein (iii) in response to at least one parallel operation program instruction word separately performing a first arithmetic logic operation upon a first (N/2)-bit input operand data word and a second arithmetic logic operation upon a second (N/2)-bit input operand data word; (iv) setting a first set of condition code flags in dependence upon said first arithmetic logic operation; and (v) setting a second set of condition code flags in dependence upon said second arithmetic logic operation wherein said arithmetic logic unit is responsive to a conditional select instruction that moves one of said first N/2)-bit input operand data words stored in a first source register and one of said first (N/2)-bit input operand data word stored in a second source register to a destination register of said plurality of registers in dependence upon said first set of condition flags and moves one of said second (N/2)-bit input operand data words stored in a first source register and one of said second (N/2)-bit input operand data words stored in a second source register to said destination register in dependence upon said second set of condition flags.