US5390135A
Expired / Lapsed
US
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Parallel shift and add circuit and method
Assignee: Hewlett Packard Development Co LP
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Filing: 1993-11-29
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Granted: 1995-02-14
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Expires: 2013-11-29
Abstract
Abstract An apparatus for combining the contents of an X register, shifted by m places, with the contents of a Y register to generate a result Z. The functional unit can also be configured to perform parallel operations on sub-operands in the X and Y registers. The division of the apparatus into sub-operands is controlled by a mask which specifies the boundary of the sub-operands. The shifting operation is accomplished by multiplexers that connect the p th bit of the X register to the adder stage that operates on bit Y p-m of the Y register. Circuitry is provided at the boundary of the sub-operands to prevent the bit signals corresponding to the X register from being routed across a sub-operand boundary. Similarly, circuitry is provided for preventing the carry output of an adder stage that operates on one sub-operand from being propagated to an adder stage that operates on another sub-operand.
Inventors
- 👤 Ruby B. Lee
- 👤 Joel D. Lamb
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:06
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/527; G06F7/5272; G06F7/50; G06F7/505; G06F7/506; G06F7/508; G06F7/57; G06F7/575; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/3001; G06F9/30014; G06F9/30036; G06F9/30038; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3828; G06F7/499; G06F7/49905; G06F7/4991; G06F7/49921; G06F7/49942; G06F7/49947; G06F7/49963
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
131 words
An apparatus for operating on the contents of an X word having bits X i and a Y word having bits Y i to generate a result word having bits Z i , where i=0 to N-1, where Z 0 is the least significant bit and Z N-1 is the most significant bit, said apparatus comprising: means for partitioning said X, Y and result words into a plurality of sub-words, there being one sub-word of said Y and result words corresponding to each sub-word of said X word; and means, responsive to a first instruction, for generating the sum of each X sub-word divided by 2 m and the corresponding Y sub-word, the result thereof determining said corresponding sub-word of said result word, wherein m is an integer different from 0.
Claim 2
Independent Claim
131 words
An apparatus for operating on the contents of an X word having bits X i and a Y word having bits Y i to generate a result word having bits Z i , where i=0 to N-1, where Z 0 is the least significant bit and Z N-1 is the most significant bit, said apparatus comprising: means for partitioning said X, Y and result words into a plurality of sub-words, there being one sub-word of said Y and result words corresponding to each sub-word of said X word; and means, responsive to a first instruction, for generating the sum of each X sub-word divided by 2 m and the corresponding Y sub-word, the result thereof determining said corresponding sub-word of said result word, wherein m is an integer different from 0.
Claim 3
Dependent Claim
47 words
The apparatus of claim 1 further comprising means, responsive to a second instruction, for generating the difference of each sub-word in said X word divided by 2 m and the corresponding sub-word in said Y word, the result thereof determining said corresponding sub-word of said result word.
Claim 4
Dependent Claim
36 words
The apparatus of claim 1 wherein the result of dividing each said sub-word in said X word is rounded to the next highest odd integer if said division by 2 m resulted in a round-off error.
Claim 5
Dependent Claim
290 words
The apparatus of claim 1 comprising multiplexing means for directing bits of said X word and adding means for adding bits derived from said X and Y words, said adding means comprising: a plurality of Y input means, each said Y input means receiving a bit derived from said Y-word, said Y-input means receiving said bit derived from Y p being referred to as the p th Y input means; a plurality of X input means, each said X input means receiving a bit derived from said X word, therebeing one said X input means corresponding to each said Y input means, said X input means corresponding to the p th Y input means being referred to as the p th X input means; and a plurality of adding stages connected in series, each adding stage comprising means for adding one or more bits of received on said X input means and the corresponding bits received on said Y input means, and means for propagating a carry bit from said adding stage to the next said adding stage in said series connection, said adding stage operating on Y p being referred to as the p th said adding stage, and wherein said partitioning means comprises means for forcing said carry bit to a value determined by the operation being performed if said adding stages operate on bits of different sub-words in said X word, and wherein said multiplexing means comprises a plurality of multiplexing circuits, there being one said multiplexing circuit connected to each said adding stage, said multiplexing circuit connected to said p th adding stage connecting said adding stage to X p+m if Y p and Y p+m are in the same said sub-word of said Y word.
Claim 6
Dependent Claim
48 words
The apparatus of claim 4 wherein said multiplexing circuit connected to said p th adding stage connects the most significant bit of one of said X sub-words to said p th adding stage if Y p and Y p+m are in different said sub-words of said Y word.
Claim 7
Dependent Claim
44 words
The apparatus of claim 4 wherein said multiplexing circuit connected to said p th adding stage connects a signal having the value 0 to said p th adding stage if Y p and Y p+m are in different said sub-words of said Y word.
Claim 8
Dependent Claim
50 words
The apparatus of claim 4 further comprising means for generating a signal having the value (X p OR X p+1 OR . . . X p+m ) and connecting said signal to said p th adding stage when Y p is the least significant bit of one of said sub-words.
Claim 9
Dependent Claim
18 words
The apparatus of claim 7 further comprising a storage cell for storing the value of said generated signal.
Claim 10
Dependent Claim
37 words
The apparatus of claim 4 wherein said partitioning means further comprises means for generating a signal indicating that one of said carry bits was a "1" prior to said carry bit being forced to said determined value.
Claim 11
Independent Claim
98 words
An apparatus for operating on the contents of an X word having bits X i and a Y word having bits Y i to generate a result word having bits Z i , where i=0 to N-1, where Z 0 is the least significant bit and Z N-1 is the most significant bit, said apparatus comprising: means, responsive to a first instruction, for generating the sum of said X word divided by 2 m and Y word; and means for generating said result word from the result of said addition, wherein m is an integer different from 0.
Claim 12
Independent Claim
98 words
An apparatus for operating on the contents of an X word having bits X i and a Y word having bits Y i to generate a result word having bits Z i , where i=0 to N-1, where Z 0 is the least significant bit and Z N-1 is the most significant bit, said apparatus comprising: means, responsive to a first instruction, for generating the sum of said X word divided by 2 m and Y word; and means for generating said result word from the result of said addition, wherein m is an integer different from 0.
Claim 13
Dependent Claim
42 words
The apparatus of claim 10 further comprising means, responsive to a second instruction, for generating the difference of said X word divided by 2 m and said Y word, the result thereof being stored in said corresponding sub-word of said result word.
Claim 14
Dependent Claim
33 words
The apparatus of claim 10 wherein the result of dividing each said X word is rounded to the next highest odd integer if said division by 2 m resulted in a round-off error.
Claim 15
Dependent Claim
241 words
The apparatus of claim 10 comprising multiplexing means for directing bits of said X word and adding means for adding bits derived from said X and Y words, said adding means comprising: a plurality of Y input means, each said Y input means receiving a bit derived from said Y-word, said Y-input means receiving said bit derived from Y p being referred to as the p th Y input means; a plurality of X input means, each said X input means receiving a bit derived from said X word, therebeing one said X input means corresponding to each said Y input means, said X input means corresponding to the p th Y input means being referred to as the p th X input means; and a plurality of adding stages connected in series, each said adding stage comprising means for adding one or more bits received on said X input means and the corresponding bits received on said Y input means, and means for propagating a carry bit from said adding stage to the next said adding stage in said series connection, said adding stage operating on Y p being referred to as the p th said adding stage, and wherein said multiplexing means comprises a plurality of multiplexing circuits, there being one said multiplexing circuit connected to each said adding stage, said multiplexing circuit connected to said p th adding stage connecting said adding stage to X p+m if p+m<N.
Claim 16
Dependent Claim
29 words
The apparatus of claim 13 wherein said multiplexing circuit connected to said p th adding stage connects said adding stage to a signal having logical value 0 if p+m>(N-1).
Claim 17
Dependent Claim
25 words
The apparatus of claim 13 wherein said multiplexing circuit connected to said p th adding stage connects said adding stage to X N-1 if p+m>(N-1).
Claim 18
Dependent Claim
37 words
The apparatus of claim 13 further comprising means for generating a signal having the value (X 0 OR X 1 OR . . . X m ) and connecting said signal to said 0 th adding stage.
References Cited (Backward Citations)
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