Switching circuit

Claim 2

A switching circuit comprising: a first transmission path; a first input/output terminal connected to one end of said first transmission path; a second input/output terminal connected to the other end of said first transmission path, said first transmission path including a first field effect transistor having a first conduction path which is connected at one end to said first input/output terminal; a second field effect transistor having a second conduction path which is connected at one end to the other end of the first conduction path of said first field effect transistor and connected at the other end to said second input/output terminal; and a first inductor connected in parallel with the first conduction path of said first field effect transistor, said second field effect transistor being devoid of a paralleled inductor; a second transmission path connected at one end thereof to said second input/output terminal; a third input/output terminal, which is isolated from said first input/output terminal, connected to the other end of said second transmission path; and means for decreasing a difference between a voltage applied to the first conduction path of said first field effect transistor and a voltage applied to the second conduction path of said second field effect transistor, when said first and said second transistors are in an OFF state.

Claim 3

A switching circuit according to claim 1, wherein said second transmission path includes a third field effect transistor having a third conduction path which is connected between said second and said third input/output terminal; and a second inductor connected in parallel with the third conduction path.

Claim 4

A switching circuit according to claim 2, wherein said first input/output terminal is connected to a reception circuit, said second input/output terminal is connected to an antenna, and said third input/output terminal is connected to a transmission circuit so as to switch high-frequency signals of reception and transmission.

Claim 5

A switching circuit according to claim 3, wherein a capacitance which said first field effect transistor has in an OFF state and said first inductor resonate at a preset frequency of the high-frequency signals.

Claim 6

A switching circuit according to claim 3, wherein a capacitance which said third field effect transistor has in an OFF state and said second inductor resonate at a preset frequency of the high-frequency signals.

Claim 7

A switching circuit according to claim 1, wherein said second input/output terminal is coupled to a reference potential via a resistor, and preset voltages applied to gate electrodes of said first and said second field effect transistor via respective preset resistors to control conduction states of the first and the second conduction path, respectively.

Claim 8

A switching circuit according to claim 1, wherein said first and said second transistor is a depletion type transistor.

Claim 9

A switching circuit according to claim 2, wherein a reference potential is applied to said second input/output terminal via a resistor and a preset voltage is applied to a gate electrode of said third field effect transistor via a preset resistor to control a conduction state of the third conduction path.

Claim 10

A switching circuit according to claim 2, wherein said third transistor is a depletion type transistor.

Claim 11

A switching circuit according to claim 1, wherein said means for decreasing a difference comprises a voltage terminal to which a preset voltage is applied and a capacitor connected between the other end of the first conduction path of said first transistor and said voltage terminal.

Claim 12

A switching circuit according to claim 1, wherein said second field effect transistor is a multi-finger type field effect transistor having a plurality of gate electrodes connected to one another.

Claim 13

A switching circuit according to claim 1, wherein said means for decreasing a difference comprises a construction such that a gate width of said second field effect transistor is smaller than a gate width of said first field effect transistor.

Claim 14

A switching circuit according to claim 11, wherein the total gate width of the plurality of gate electrodes of said second field effect transistor is smaller than a gate width of said first field effect transistor.

Claim 15

A switching circuit according to claim 1, wherein said means for decreasing a difference comprises a voltage terminal to which a preset voltage is applied and a fourth transistor having a fourth conduction path connected between the other end of the first conduction path of said first transistor and said voltage terminal to which the preset voltage is applied.

Claim 16

A switching circuit comprising: a first input/output terminal; a first field effect transistor having a first source electrode connected to said first input/output terminal, a first drain electrode and a first gate electrode; a first inductor connected between the first source electrode and the first drain electrode; a second field effect transistor having a second source electrode connected to the first drain electrode, a second drain electrode and a second gate electrode; a first control terminal for controlling conduction states of said first and said second field effect transistor; a first resistor connected between said first control terminal and the first gate electrode; a second resistor connected between said first control terminal and the second gate electrode; a second input/output terminal connected to the second drain electrode; a first voltage terminal for applying a reference potential; a third resistor connected between said voltage terminal and said second input/output terminal; a third field effect transistor having a third source electrode connected to said second input/output terminal, a third drain electrode and a third gate electrode; a second inductor connected between the third source electrode and the third drain electrode; a third input/output terminal connected to the third drain electrode; a second control terminal for controlling a conduction state of said third field effect transistor; and a fourth resistor connected between said second control terminal and the third gate electrode.

Claim 17

A switching circuit comprising: a first input/output terminal; a first field effect transistor having a first source electrode connected to said first input/output terminal, a first drain electrode and a first gate electrode; a first inductor connected between the first source electrode and the first drain electrode; a second field effect transistor having a second source electrode connected to the first drain electrode, a second drain electrode and a second gate electrode; a first control terminal for controlling conduction states of said first and said second field effect transistor; a first resistor connected between said first control terminal and the first gate electrode; a second resistor connected between said first control terminal and the second gate electrode; a second input/output terminal connected to the second drain electrode; a first voltage terminal for applying a reference potential; a third resistor connected between said voltage terminal and said second input/output terminal; a third field effect transistor having a third source electrode connected to said second input/output terminal, a third drain electrode and a third gate electrode; a second inductor connected between the third source electrode and the third drain electrode; a third input/output terminal connected to the third drain electrode; a second control terminal for controlling a conduction state of said third field effect transistor; and a fourth resistor connected between said second control terminal and the third gate electrode.

Claim 18

A switching circuit according to claim 15, further comprising a second voltage terminal for applying a preset voltage and a capacitor connected between the first drain electrode and said second voltage terminal.

Claim 19

A switching circuit according to claim 15, wherein said second field effect transistor is a multi-finger type field effect transistor having a plurality of gate electrodes connected to one another.

Claim 20

A switching circuit according to claim 15, wherein a gate width of said second field effect transistor is smaller than a gate width of said first field effect transistor.

Claim 21

A switching circuit according to claim 17, wherein the total gate width of the plurality of gate electrodes of said second field effect transistor is smaller than a gate width of said first field effect transistor.

Claim 22

A switching circuit according to claim 15, further comprising a third voltage terminal for applying a preset voltage and a fourth field effect transistor having a fourth source electrode connected to said third voltage terminal, a fourth drain electrode connected to the first drain electrode, and a fourth gate electrode.