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Patent US5745672A successfully refreshed from Google Patents.
US5745672A
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Main memory system and checkpointing protocol for a fault-tolerant computer system using a read buffer
Assignee: Radisys Corp
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Filing: 1995-11-29
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Granted: 1998-04-28
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Expires: 2015-11-29
Abstract
Abstract A mechanism for maintaining a consistent, periodically updated state in main memory without constraining normal computer operation is provided, thereby enabling a computer system to recover from faults without loss of data or processing continuity. In a typical computer system, a processor and input/output elements are connected to a main memory subsystem that includes a primary memory. In embodiments of the present invention, a read buffer is also appended to this main memory subsystem. During normal processing, a pre-image of data written to the primary memory may be captured by the read buffer. Data captured in the read buffer can restore the system to a previous checkpoint. This structure and protocol can guarantee a consistent state in main memory, thus enabling fault-tolerant operation.
Inventors
- 👤 Jack J. Stiffler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 19:49
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1405; G06F11/1407
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
142 words
A computer system comprising: a processor: and a main memory subsystem coupled to the processor wherein the main memory subsystem includes: a primary memory element to which data is written and from which data is read; a read buffer coupled to the primary memory element, that captures and stores data read from the primary memory element; and a shadow memory, coupled to the main memory subsystem, that receives data written to the main memory subsystem and stores the data simultaneously with the primary memory element; and means for copying the data from the read buffer to the primary memory element and the shadow memory in response to an instruction from the processor, so that the main memory subsystem can be returned to a consistent checkpoint state from which processing can resume without loss of data integrity or program continuity following a fault.
Claim 2
Dependent Claim
142 words
A computer system comprising: a processor: and a main memory subsystem coupled to the processor wherein the main memory subsystem includes: a primary memory element to which data is written and from which data is read; a read buffer coupled to the primary memory element, that captures and stores data read from the primary memory element; and a shadow memory, coupled to the main memory subsystem, that receives data written to the main memory subsystem and stores the data simultaneously with the primary memory element; and means for copying the data from the read buffer to the primary memory element and the shadow memory in response to an instruction from the processor, so that the main memory subsystem can be returned to a consistent checkpoint state from which processing can resume without loss of data integrity or program continuity following a fault.
Claim 3
Dependent Claim
132 words
A computer system comprising: a processor; and a main memory subsystem coupled to the processor, wherein the main memory subsystem includes: a primary memory element to which data is written and from which data is read; a read buffer, coupled to the primary memory element, that captures and stores data read from the primary memory element and including means for ensuring that a premodified version of all data to be modified during any interval between checkpoints has been captured in the read buffer during that same interval and means for copying the data from the read buffer to the primary memory element, so that the main memory subsystem can be returned to a consistent checkpoint state from which processing can resume without loss of data integrity or program continuity following a fault.
Claim 4
Dependent Claim
132 words
A computer system comprising: a processor; and a main memory subsystem coupled to the processor, wherein the main memory subsystem includes: a primary memory element to which data is written and from which data is read; a read buffer, coupled to the primary memory element, that captures and stores data read from the primary memory element and including means for ensuring that a premodified version of all data to be modified during any interval between checkpoints has been captured in the read buffer during that same interval and means for copying the data from the read buffer to the primary memory element, so that the main memory subsystem can be returned to a consistent checkpoint state from which processing can resume without loss of data integrity or program continuity following a fault.
Claim 5
Dependent Claim
134 words
A computer system comprising: a processor; and a main memory subsystem coupled to the processor, wherein the main memory subsystem includes: a primary memory element to which data is written and from which data is read; a read buffer, coupled to the primary memory element, that captures and stores data read from the primary memory element and including means for determining whether the data read from memory will be modified, and for storing in the read buffer only data that will be modified during any given interval between checkpoints; and means for copying the data from the read buffer to the primary memory element, so that the main memory subsystem can be returned to a consistent checkpoint state from which processing can resume without loss of data integrity or program continuity following a fault.
Claim 6
Dependent Claim
134 words
A computer system comprising: a processor; and a main memory subsystem coupled to the processor, wherein the main memory subsystem includes: a primary memory element to which data is written and from which data is read; a read buffer, coupled to the primary memory element, that captures and stores data read from the primary memory element and including means for determining whether the data read from memory will be modified, and for storing in the read buffer only data that will be modified during any given interval between checkpoints; and means for copying the data from the read buffer to the primary memory element, so that the main memory subsystem can be returned to a consistent checkpoint state from which processing can resume without loss of data integrity or program continuity following a fault.
Claim 7
Dependent Claim
39 words
The computer system of claim 3, wherein the means for determining includes means for determining whether data to be modified has previously been modified in a given checkpoint interval and storing only a first premodified copy of that data.
Claim 8
Dependent Claim
150 words
A computer system comprising: a processor having a cache, internal registers and an input/output event queue; and a main memory subsystem coupled to the processor, wherein the main memory subsystem includes: a primary memory element to which data is written and from which data is read; a read buffer, coupled to the primary memory element, that captures and stores data read from the primary memory element; means for copying the data from the read buffer to the primary memory element, so that the main memory subsystem can be returned to a consistent checkpoint state from which processing can resume without loss of data integrity or program continuity following a fault, and wherein the processor periodically flushes the cache, internal registers and input/output event queue, and upon completion of the flushing, establishes a checkpoint and instructs the read buffer memory to discard all data previously stored in the read buffer memory.
Claim 9
Dependent Claim
150 words
A computer system comprising: a processor having a cache, internal registers and an input/output event queue; and a main memory subsystem coupled to the processor, wherein the main memory subsystem includes: a primary memory element to which data is written and from which data is read; a read buffer, coupled to the primary memory element, that captures and stores data read from the primary memory element; means for copying the data from the read buffer to the primary memory element, so that the main memory subsystem can be returned to a consistent checkpoint state from which processing can resume without loss of data integrity or program continuity following a fault, and wherein the processor periodically flushes the cache, internal registers and input/output event queue, and upon completion of the flushing, establishes a checkpoint and instructs the read buffer memory to discard all data previously stored in the read buffer memory.
Claim 10
Dependent Claim
57 words
The computer system of claim 3, wherein the read buffer memory is a last in first out memory, so that when the read buffer memory is read, data previously written into the memory is read from the buffer memory in a reverse order from an order in which the data was written into the read buffer memory.
Claim 11
Dependent Claim
167 words
A computer system comprising: a processor; an input/output port; a main memory subsystem coupled to the processor and to the input/output port, wherein the main memory subsystem includes: a primary memory element to which data is written and from which data is read; a read buffer, coupled to the primary memory element, that captures and stores data read from the primary memory element; and means for copying the data from the read buffer to the primary memory element, so that the main memory subsystem can be returned to a consistent checkpoint state from which processing can resume without loss of data integrity or program continuity following a fault, wherein each processor has a corresponding input/output subsystem which provides input/output events initiated by the processor, wherein each processor has means for queuing input/output events between checkpoints and means for flushing the queued events to the main memory subsystem when a checkpoint is to be established, whereby input/output events are captured in checkpoint data in the main memory subsystem.
Claim 12
Dependent Claim
167 words
A computer system comprising: a processor; an input/output port; a main memory subsystem coupled to the processor and to the input/output port, wherein the main memory subsystem includes: a primary memory element to which data is written and from which data is read; a read buffer, coupled to the primary memory element, that captures and stores data read from the primary memory element; and means for copying the data from the read buffer to the primary memory element, so that the main memory subsystem can be returned to a consistent checkpoint state from which processing can resume without loss of data integrity or program continuity following a fault, wherein each processor has a corresponding input/output subsystem which provides input/output events initiated by the processor, wherein each processor has means for queuing input/output events between checkpoints and means for flushing the queued events to the main memory subsystem when a checkpoint is to be established, whereby input/output events are captured in checkpoint data in the main memory subsystem.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-04-27 | 2001-10-27 | 2002-04-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-04-27 | 2005-10-27 | 2006-04-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-04-27 | 2009-10-27 | 2010-04-28 | $7700.00 | Window Closed / Lapsed |