High-speed, low-current magnetoresistive memory device

Claim 2

A magnetoresistive memory device for storing binary information, comprising: at least one memory cell having a first memory element and a second memory element, each of these memory elements separately having at least two ferromagnetic layers that collectively exhibit one electrical resistance when magnetized in a parallel state and a different electrical resistance when magnetized in an antiparallel state, and each of these memory elements separately having a writing electrode for the passage of a current generating a magnetic field capable of switching said ferromagnetic layers between said parallel state and said antiparallel state; a write access circuit coupled to said memory cell, for supplying current to each said writing electrode in said memory cell, responsive to said binary information, thereby storing a first binary value in said memory cell by setting the ferromagnetic layers in said first memory element to said parallel state and the ferromagnetic layers in said second memory element to said antiparallel state, and storing a second binary value in said memory cell by setting the ferromagnetic layers in said first memory element to said antiparallel state and the ferromagnetic layers in said second memory element to said parallel state; and a read access circuit coupled to said memory cell, for comparing the electrical resistance of the ferromagnetic layers in said first memory element with the electrical resistance of the ferromagnetic layers in said second memory element, thereby reading the binary value stored in said memory cell.

Claim 3

The magnetoresistive memory device of claim 1, wherein each of said memory elements comprises at least one antiferromagnetic layer for pinning a respective one of said ferromagnetic layers in a certain magnetization state.

Claim 4

The magnetoresistive memory device of claim 1, wherein said ferromagnetic layers have different coercivities.

Claim 5

The magnetoresistive memory device of claim 1, wherein said writing electrode of said first memory element and said writing electrode of said second memory element are coupled in series.

Claim 6

The magnetoresistive memory device of claim 1, comprising a plurality of memory cells as described in claim 1, disposed in an array having rows and columns, and further comprising: a plurality of first signal lines disposed in respective rows, coupling said write access circuit to said memory cells; a plurality of second signal lines disposed in respective columns, coupling said write access circuit to said memory cells; a plurality of third signal lines disposed in respective rows, coupling said read access circuit to said memory cells; a plurality of fourth signal lines disposed in respective columns, coupling said read access circuit to said memory cells; and a plurality of fifth signal lines disposed in respective columns, coupling said read access circuit to said memory cells; wherein said write access circuit selectively supplies said current to the writing electrode of an arbitrary one of said memory cells through a corresponding one of said first signal lines and a corresponding one of said second signal lines.

Claim 7

The magnetoresistive memory device of claim 5, wherein in each of said memory cells, the ferromagnetic layers of said first memory element and the ferromagnetic layers of said second memory element are both coupled to a single one of said third signal lines, the ferromagnetic layers of said first memory element are coupled to one of said fourth signal lines, and the ferromagnetic layers of said second memory element are coupled to one of said fifth signal lines.

Claim 8

The magnetoresistive memory device of claim 6, wherein said read access circuit reads the binary value stored in an arbitrary one of said memory cells by supplying a certain current to a corresponding one of said third signal lines and comparing resulting voltages on a corresponding one of said fourth signal lines and a corresponding one of said fifth signal lines.

Claim 9

The magnetoresistive memory device of claim 6, wherein said read access circuit reads the binary value stored in an arbitrary one of said memory cells by supplying a certain voltage to a corresponding one of said third signal lines and comparing resulting currents on a corresponding one of said fourth signal lines and a corresponding one of said fifth signal lines.

Claim 10

A magnetoresistive memory device for storing binary information in an array of rows and columns, comprising: a plurality of first signal lines disposed in respective rows; a plurality of second signal lines disposed in respective columns; a plurality of third signal lines disposed in respective rows; a plurality of fourth signal lines disposed in respective columns; a plurality of memory elements disposed at intersections of respective rows and columns, each of said memory elements separately having at least two ferromagnetic layers electrically coupled to one of said third signal lines and one of said fourth signal lines, that collectively exhibit one electrical resistance when magnetized in a parallel state and a different electrical resistance when magnetized in an antiparallel state, and each of said memory elements separately having a writing electrode electrically coupled to a corresponding one of said first signal lines and a corresponding one of said second signal lines, for the passage of a current generating a magnetic field capable of switching said ferromagnetic layers between said parallel state and said antiparallel state; a write access circuit coupled to said first signal lines and said second signal lines, for supplying current to the writing electrode in an arbitrary one of said memory elements, responsive to said binary information, thereby storing a first binary value by setting the ferromagnetic layers in said one of said memory elements to said parallel state, and storing a second binary value by setting the ferromagnetic layers in said one of said memory elements to said antiparallel state; and a read access circuit coupled to said third signal lines and said fourth signal lines, for detecting the electrical resistance of the ferromagnetic layers in said memory elements, thereby reading the binary information stored in said memory elements.

Claim 11

A magnetoresistive memory device for storing binary information in an array of rows and columns, comprising: a plurality of first signal lines disposed in respective rows; a plurality of second signal lines disposed in respective columns; a plurality of third signal lines disposed in respective rows; a plurality of fourth signal lines disposed in respective columns; a plurality of memory elements disposed at intersections of respective rows and columns, each of said memory elements separately having at least two ferromagnetic layers electrically coupled to one of said third signal lines and one of said fourth signal lines, that collectively exhibit one electrical resistance when magnetized in a parallel state and a different electrical resistance when magnetized in an antiparallel state, and each of said memory elements separately having a writing electrode electrically coupled to a corresponding one of said first signal lines and a corresponding one of said second signal lines, for the passage of a current generating a magnetic field capable of switching said ferromagnetic layers between said parallel state and said antiparallel state; a write access circuit coupled to said first signal lines and said second signal lines, for supplying current to the writing electrode in an arbitrary one of said memory elements, responsive to said binary information, thereby storing a first binary value by setting the ferromagnetic layers in said one of said memory elements to said parallel state, and storing a second binary value by setting the ferromagnetic layers in said one of said memory elements to said antiparallel state; and a read access circuit coupled to said third signal lines and said fourth signal lines, for detecting the electrical resistance of the ferromagnetic layers in said memory elements, thereby reading the binary information stored in said memory elements.

Claim 12

The magnetoresistive memory device of claim 9, wherein each of said memory elements comprises at least one antiferromagnetic layer for pinning a respective one of said ferromagnetic layers in a certain magnetization state.

Claim 13

The magnetoresistive memory device of claim 9, wherein said ferromagnetic layers have different coercivities.

Claim 14

The magnetoresistive memory device of claim 9, wherein said read access circuit reads the binary value stored in an arbitrary one of said memory elements by supplying a certain current to a corresponding one of said third signal lines and detecting a resulting voltage on a corresponding one of said fourth signal lines.

Claim 15

The magnetoresistive memory device of claim 9, wherein said read access circuit reads the binary value stored in an arbitrary one of said memory elements by supplying a certain voltage to a corresponding one of said third signal lines and detecting a resulting current on a corresponding one of said fourth signal lines.

Claim 18

The method of claim 14 wherein, in said step of storing a first binary value and said step of storing a second binary value, a single current is supplied to both the writing electrode of said first memory element and the writing electrode of said second memory element, these writing electrodes being coupled in series.

Claim 19

The method of claim 14 wherein said step of reading comprises the further steps of: supplying parallel currents to said first memory element and said second memory element; and comparing voltages produced by passage of said parallel currents through said first memory element and said second memory element.

Claim 20

The method of claim 14, wherein said step of reading comprises the further steps of: supplying equal voltages to said first memory element and said second memory element; and comparing resulting currents flowing through said first memory element and said second memory element.

Claim 23

The method of claim 18, wherein said step of reading comprises the further steps of: supplying a certain current to said memory element; and detecting a voltage produced by passage of said current through said memory element.

Claim 24

The method of claim 18, wherein said step of reading comprises the further steps of: supplying a certain voltage to said memory element; and detecting a current flowing through said memory element.