DC-to-DC converter functioning in a pulse-skipping mode with low power consumption and PWM inhibit

Claim 3

A method as defined in claim 1, wherein said inhibiting is implemented by masking the switching to a logic "0" of a high frequency timing signal of the converter for the entire period of time said current remains below said minimum threshold value.

Claim 4

The method of claim 1, wherein said converter is a buck converter.

Claim 5

The method of claim 1, wherein said minimum threshold value is defined by sensing the voltage drop across a resistor which is in series with the inductor.

Claim 6

The method of claim 1, wherein said reduction of the overall switching frequency is accomplished by pulse skipping.

Claim 7

The method of claim 1, wherein said inhibiting step is performed without inhibiting clock pulses.

Claim 8

The method of claim 1, wherein said inhibiting step is performed by inhibiting clock pulses.

Claim 9

A DC-to-DC static converter composed of a power section which comprises at least a switch driven at a switching frequency set by a clock or local oscillator signal, an inductor, a discharge diode, an output storage capacitor, a PWM control loop suitable to control the duty-cycle of said switch by commanding the turning off in function of the current level in the inductor and of the output voltage of the converter, and a control circuit for reducing the overall switching frequency during idle periods as long as the current in the inductor remains below a minimum threshold value set by a comparator, comprising logic means capable of inhibiting any turn-off command of said PWM control loop switch of the converter for as long as the current in the inductor remains below said minimum threshold value.

Claim 10

A DC-to-DC static converter composed of a power section which comprises at least a switch driven at a switching frequency set by a clock or local oscillator signal, an inductor, a discharge diode, an output storage capacitor, a PWM control loop suitable to control the duty-cycle of said switch by commanding the turning off in function of the current level in the inductor and of the output voltage of the converter, and a control circuit for reducing the overall switching frequency during idle periods as long as the current in the inductor remains below a minimum threshold value set by a comparator, comprising logic means capable of inhibiting any turn-off command of said PWM control loop switch of the converter for as long as the current in the inductor remains below said minimum threshold value.

Claim 11

The converter of claim 8, wherein said switch is a power field-effect transistor.

Claim 12

A converter as defined in claim 4, wherein said logic means mask the transition to "0" of said clock or local oscillator signal.

Claim 15

The method of claim 11, wherein said transistor is a power field-effect transistor.

Claim 16

The method of claim 11, wherein said inhibiting step is performed without inhibiting clock pulses.

Claim 17

The method of claim 11, wherein said sensing step uses a resistor which is connected in series with said inductor, and a comparator connected to sense the voltage across said resistor.

Claim 18

The method of claim 11, wherein said inductor is connected in a buck converter configuration.

Claim 19

A power converter circuit comprising: a load connection for applying an electrical power output to a load; at least one inductor element, and a switching transistor connected to drive said inductor element; sensing circuitry which senses the current through said inductor element; and a pulse-width modulator circuit, operatively connected to receive an input from said sensing element, and operatively connected to repeatedly switch said transistor, under normal conditions, to provide at least a desired level of output to said load connection; and further comprising inhibit logic operatively connected to prevent said transistor from turning off, under low load conditions, for as long as the current through said inductor is below a threshold value.

Claim 20

A power converter circuit comprising: a load connection for applying an electrical power output to a load; at least one inductor element, and a switching transistor connected to drive said inductor element; sensing circuitry which senses the current through said inductor element; and a pulse-width modulator circuit, operatively connected to receive an input from said sensing element, and operatively connected to repeatedly switch said transistor, under normal conditions, to provide at least a desired level of output to said load connection; and further comprising inhibit logic operatively connected to prevent said transistor from turning off, under low load conditions, for as long as the current through said inductor is below a threshold value.

Claim 21

The circuit of claim 16, wherein said sensing circuitry comprises a resistor which is connected in series with said inductor, and a comparator connected to sense the voltage across said resistor.

Claim 22

The circuit of claim 16, wherein said transistor is a power field-effect transistor.

Claim 23

The circuit of claim 16, wherein said inductor is connected in a buck converter configuration.

Claim 24

A static DC-to-DC converter composed of a power section which comprises at least a switch switching at a frequency set by a clock or local oscillator timing signal, an inductor, a discharge diode and an output storage capacitor charged by the discharge current of said inductor, a PWM control loop comprising an error amplifier and a comparator for controlling the duty-cycle of said switch in function of the current in the inductor as detected by a sensing resistance and the output voltage on said storage capacitor, a flip-flop driving said switch and having a "set" input to receive said timing signal and a reset input for receiving a control signal produced by said PWM control loop, at least a second comparator, the inputs of which are functionally connected to said sensing resistance, characterized by comprising a first OR logic circuit having a first input connected to the output of said second comparator, a second input to which a drive signal of said switch is applied and an output; a second AND logic circuit having a first input connected to the output of said first OR logic circuit, a second input connected to an output of said PWM control loop and an output connected to said reset input of said driving flip-flop; a third NAND logic circuit having a first input connected to the output of said first OR logic circuit, a second input connected to said set input of said flip-flop and an output; a fourth NAND logic circuit having an input connected to an output of said flip-flop, a second input connected to the output of said third NAND logic circuit and an output connected to a control terminal of said switch.

Claim 25

A static DC-to-DC converter composed of a power section which comprises at least a switch switching at a frequency set by a clock or local oscillator timing signal, an inductor, a discharge diode and an output storage capacitor charged by the discharge current of said inductor, a PWM control loop comprising an error amplifier and a comparator for controlling the duty-cycle of said switch in function of the current in the inductor as detected by a sensing resistance and the output voltage on said storage capacitor, a flip-flop driving said switch and having a "set" input to receive said timing signal and a reset input for receiving a control signal produced by said PWM control loop, at least a second comparator, the inputs of which are functionally connected to said sensing resistance, characterized by comprising a first OR logic circuit having a first input connected to the output of said second comparator, a second input to which a drive signal of said switch is applied and an output; a second AND logic circuit having a first input connected to the output of said first OR logic circuit, a second input connected to an output of said PWM control loop and an output connected to said reset input of said driving flip-flop; a third NAND logic circuit having a first input connected to the output of said first OR logic circuit, a second input connected to said set input of said flip-flop and an output; a fourth NAND logic circuit having an input connected to an output of said flip-flop, a second input connected to the output of said third NAND logic circuit and an output connected to a control terminal of said switch.