US5629610A — Dual threshold current mode digital PWM controller

Claim 1

Independent Claim 58 words

A method for driving a power output terminal, comprising the steps of: (a.) sensing an input current, and accordingly (b.) using a first open loop, activating a switching transistor when said input current falls below a first threshold, and (c.) using a second open loop, disabling said switching transistor when said input current rises above a second threshold.

Claim 2

Independent Claim 58 words

A method for driving a power output terminal, comprising the steps of: (a.) sensing an input current, and accordingly (b.) using a first open loop, activating a switching transistor when said input current falls below a first threshold, and (c.) using a second open loop, disabling said switching transistor when said input current rises above a second threshold.

Claim 3

Dependent Claim 15 words

The method of claim 1, wherein said switching transistor is a power field effect transistor.

Claim 4

Dependent Claim 44 words

The method of claim 1, wherein said switching transistor is a power field effect transistor having one terminal thereof connected to a boosting capacitor, which is connected in a charge-pumping configuration to provide a boosted supply voltage to the gate of said power transistor.

Claim 5

Dependent Claim 157 words

A digital, current mode, PWM control circuit for an output stage comprising a sensing resistance of an input current connected in series with a power switch of the output stage, a bistable driving circuit having a clock input suitable to receive a PWM clock signal and a reset input driven by an output of a multi-input logic circuit, comprising: at least a first comparator of the voltage on said sensing resistance having a certain threshold and an output connected to a first input of said logic circuit; at least a second comparator of the voltage on said sensing resistance, having a threshold higher than the threshold of said first comparator and an output connected to a second input of said logic circuit; means driven by the output of said second comparator capable of generating a logic signal for disabling said power switch for a preset period of time, fed to a third input of said logic circuit.

Claim 6

Dependent Claim 157 words

A digital, current mode, PWM control circuit for an output stage comprising a sensing resistance of an input current connected in series with a power switch of the output stage, a bistable driving circuit having a clock input suitable to receive a PWM clock signal and a reset input driven by an output of a multi-input logic circuit, comprising: at least a first comparator of the voltage on said sensing resistance having a certain threshold and an output connected to a first input of said logic circuit; at least a second comparator of the voltage on said sensing resistance, having a threshold higher than the threshold of said first comparator and an output connected to a second input of said logic circuit; means driven by the output of said second comparator capable of generating a logic signal for disabling said power switch for a preset period of time, fed to a third input of said logic circuit.

Claim 7

Dependent Claim 43 words

A control circuit as defined in claim 4, wherein said means comprise a bistable logic circuit having at least a reset input driven by a time counter which is activated by said disabling logic signal generated on an output of said bistable circuit.

Claim 8

Dependent Claim 54 words

A control circuit as defined in claim 5, wherein said bistable circuit is a D-type flip-flop having an input connected to a supply node, an output connected to said third input of said logic circuit, an input connected to the output of said second comparator and a reset input driven by said time counter.

Claim 9

Dependent Claim 55 words

A control circuit as defined in claim 6, wherein said time counter comprises a clock frequency divider circuit, which is enabled by the signal present on said output of said flip-flop and capable of generating a reset signal of said flip-flop, after a preset number of clock's cycles from a transition instant of said output.

Claim 10

Dependent Claim 80 words

A control circuit as defined in claim 7, wherein the clock frequency divider circuit comprises: a first clock frequency divider circuit generating a PWM clock frequency signal which is fed to said clock input of said driving bistable circuit; said PWM clock signal being applied to the input of a second clock frequency divider circuit activated by the transition of said output of said flip-flop capable of generating a reset signal for said flip-flop after a preset number of cycles.

Claim 11

Dependent Claim 50 words

A control circuit as defined in claim 8, further comprising an edge detector of a transition from a low logic state to a high logic state of said output of said flip-flop and capable of generating a reset signal fed to a reset input of said clock frequency divider circuit.

Claim 12

Dependent Claim 17 words

A control circuit as defined in claim 4, wherein said driving bistable circuit is a D-type flip-flop.

Claim 13

Dependent Claim 17 words

A control circuit as defined in claim 4, wherein said multi-input logic circuit is a NOR gate.

Claim 14

Dependent Claim 33 words

A control circuit as defined in claim 4, further comprising a comparator for controlling the output voltage, which generates an overvoltage limiting logic signal applicable to a fourth input of said logic circuit.

Claim 15

Dependent Claim 112 words

A switched power output subsystem, comprising: a switching transistor operatively connected between a first power supply terminal and a power output terminal; at least one reactance, connected to provide a smoothed current at said output terminal; a pulse generation circuit, operatively connected to apply pulses to a control terminal of said transistor in dependence on at least one control signal; a first control loop which compares the current at said first power supply terminal against a first threshold and selectively activates said pulse generation circuit accordingly; a second control loop which compares the current at said first power supply terminal against a second threshold and selectively blocks said pulse generation circuit accordingly.

Claim 16

Dependent Claim 112 words

A switched power output subsystem, comprising: a switching transistor operatively connected between a first power supply terminal and a power output terminal; at least one reactance, connected to provide a smoothed current at said output terminal; a pulse generation circuit, operatively connected to apply pulses to a control terminal of said transistor in dependence on at least one control signal; a first control loop which compares the current at said first power supply terminal against a first threshold and selectively activates said pulse generation circuit accordingly; a second control loop which compares the current at said first power supply terminal against a second threshold and selectively blocks said pulse generation circuit accordingly.

Claim 17

Dependent Claim 11 words

The subsystem of claim 13, wherein said reactance comprises an inductor.

Claim 18

Dependent Claim 12 words

The subsystem of claim 13, wherein said reactance is an LC circuit.

Claim 19

Dependent Claim 15 words

The subsystem of claim 13, wherein said switching transistor is a power field effect transistor.

Claim 20

Dependent Claim 44 words

The subsystem of claim 13, wherein said switching transistor is a power field effect transistor having one terminal thereof connected to a boosting capacitor, which is connected in a charge-pumping configuration to provide a boosted supply voltage to the gate of said power transistor.

Claim 21

Dependent Claim 152 words

A switched power output subsystem, comprising: a switching transistor operatively connected between a first power supply terminal and a power output terminal; at least one reactance, connected to provide a smoothed current at said output terminal; a pulse generation circuit, operatively connected to apply fixed-frequency variable-duration pulses to a control terminal of said transistor in dependence on at least one control signal; a first control loop which compares the current at said first power supply terminal against a first threshold and selectively activates said pulse generation circuit accordingly; a second control loop which compares the current at said first power supply terminal against a second threshold and selectively blocks said pulse generation circuit against activation by said first control loop accordingly; a third control loop which monitors the voltage at said output terminal and selectively activates said pulse generation circuit accordingly; wherein said first and second control loops are both open loops.

Claim 22

Dependent Claim 152 words

A switched power output subsystem, comprising: a switching transistor operatively connected between a first power supply terminal and a power output terminal; at least one reactance, connected to provide a smoothed current at said output terminal; a pulse generation circuit, operatively connected to apply fixed-frequency variable-duration pulses to a control terminal of said transistor in dependence on at least one control signal; a first control loop which compares the current at said first power supply terminal against a first threshold and selectively activates said pulse generation circuit accordingly; a second control loop which compares the current at said first power supply terminal against a second threshold and selectively blocks said pulse generation circuit against activation by said first control loop accordingly; a third control loop which monitors the voltage at said output terminal and selectively activates said pulse generation circuit accordingly; wherein said first and second control loops are both open loops.

Claim 23

Dependent Claim 12 words

The subsystem of claim 18, wherein said reactance is an LC circuit.

Claim 24

Dependent Claim 15 words

The subsystem of claim 18, wherein said switching transistor is a power field effect transistor.

Claim 25

Dependent Claim 44 words

The subsystem of claim 18, wherein said switching transistor is a power field effect transistor having one terminal thereof connected to a boosting capacitor, which is connected in a charge-pumping configuration to provide a boosted supply voltage to the gate of said power transistor.

Claim 26

Dependent Claim 11 words

The subsystem of claim 18, wherein said reactance comprises an inductor.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2000-05-12	2000-11-11	2001-05-13	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2004-05-12	2004-11-11	2005-05-13	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2008-05-12	2008-11-11	2009-05-13	$7700.00	Window Closed / Lapsed

Dual threshold current mode digital PWM controller

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