Area-efficient VDD-to-VSS ESD protection circuit

Claim 2

An electrostatic discharge (ESD) protection circuit which forms part of an integrated circuit having a VDD line and a VSS line, said protection circuit comprising: an ESD transient detection circuit connected between the VDD and VSS lines; and an electrostatic discharge circuit driven by said transient detection circuit and connected between said VDD and VSS lines, wherein said discharge circuit comprises a lateral bipolar transistor having an emitter and a collector, one of which is electrically connected to the VDD line and the other of which is electrically connected to the VSS line, wherein said lateral bipolar transistor is implemented by a field oxide device, and wherein said bipolar transistor has a base that is electrically coupled to the transient detection circuit.

Claim 3

The electrostatic discharge protection circuit of claim 1 wherein the emitter region and the collector regions are connected directly to their respective VDD and VSS lines.

Claim 4

The electrostatic protection circuit of claim 1 wherein the field oxide device has a drain region, a source region, and a channel region therebetween, said channel region being covered by a field oxide layer.

Claim 5

The electrostatic protection circuit of claim 3 wherein the channel region is sufficiently narrow to enable the field oxide device to operate as said bipolar transistor.

Claim 6

The electrostatic protection circuit of claim 4 wherein the field oxide device further comprises a well region extending below the source region, said well region having the same conduction type as the source region.

Claim 7

The electrostatic protection circuit of claim wherein the field-oxide device is an n-type field oxide device.

Claim 8

The electrostatic protection circuit of claim 6 wherein the electrostatic discharge circuit is formed in a p-type substrate and wherein the field oxide device comprises: a p-type region extending into the p-type substrate; a first n-type region extending into the p-type substrate, said first n-type region surrounding and spatially separated from the p-type region; a second n-type region extending into the p-type substrate, said second n-type region surrounding and spatially separated from the first n-type region; and an oxide layer bridging between the first and second n-type regions.

Claim 9

The electrostatic protection circuit of claim 7 wherein the field oxide device further comprises a third n-type region passing through and extending below the second n-type region to form an n-type well structure.

Claim 10

The electrostatic protection circuit of claim 8 wherein the third n-type region surrounds the first n-type region.

Claim 11

The electrostatic protection circuit of claim 9 wherein the field oxide device further comprises a second p-type region extending into the p-type substrate, said second p-type region surrounding said second n-type region.

Claim 12

The electrostatic protection circuit of claim 10 wherein the first and second n-type regions are doped to n+ doping levels.

Claim 13

The electrostatic protection circuit of claim 11 wherein the first mentioned p-type region is doped to a p+ doping level.

Claim 14

The electrostatic protection circuit of claim 6 wherein the electrostatic discharge circuit is formed in a n-type substrate and wherein the field oxide device comprises: a p-well region formed in the n-type substrate; a p-type region extending into the p-well region; a first n-type region extending into the p-well region, said first n-type region surrounding and spatially separated from the p-type region; a second n-type region extending into the p-well region, said second n-type region surrounding and spatially separated from the first n-type region; and an oxide layer bridging between the first and second n-type regions.

Claim 15

The electrostatic protection circuit of claim 13 wherein the first and second n-type regions are doped to n+ doping levels.

Claim 16

The electrostatic protection circuit of claim 14 wherein the first mentioned p-type region is doped to a p+ doping level.

Claim 17

An electrostatic discharge protection circuit which forms part of an integrated circuit having a VDD line and a VSS line, said protection circuit comprising: an ESD transient detection circuit connected between the VDD and VSS lines; and an electrostatic discharge circuit electrically coupled to said transient detection circuit and connected between said VDD and VSS lines, wherein said discharge circuit comprises a bipolar transistor having an emitter and a collector, one of which is electrically connected to the VDD line and the other of which is electrically connected to the VSS line, wherein said bipolar transistor is implemented by a vertical bipolar transistor and a field oxide device, said bipolar transistor said vertical bipolar transistor is a p-n-p device; and wherein said electrostatic discharge circuit is formed in a p-type substrate and said vertical bipolar transistor comprises: an n-well region extending into said p-type substrate; an n-type region extending into said n-well region; a first p-type region extending into said n-well region, said first p-type region surrounding and spatially separated from the n-type region and forming an emitter of said vertical bipolar transistor; and a second p-type region extending into said p-type substrate, said second p-type region surrounding and spatially separated from the n-well region.

Claim 18

An electrostatic discharge protection circuit which forms part of an integrated circuit having a VDD line and a VSS line, said protection circuit comprising: an ESD transient detection circuit connected between the VDD and VSS lines; and an electrostatic discharge circuit electrically coupled to said transient detection circuit and connected between said VDD and VSS lines, wherein said discharge circuit comprises a bipolar transistor having an emitter and a collector, one of which is electrically connected to the VDD line and the other of which is electrically connected to the VSS line, wherein said bipolar transistor is implemented by a vertical bipolar transistor and a field oxide device, said bipolar transistor said vertical bipolar transistor is a p-n-p device; and wherein said electrostatic discharge circuit is formed in a p-type substrate and said vertical bipolar transistor comprises: an n-well region extending into said p-type substrate; an n-type region extending into said n-well region; a first p-type region extending into said n-well region, said first p-type region surrounding and spatially separated from the n-type region and forming an emitter of said vertical bipolar transistor; and a second p-type region extending into said p-type substrate, said second p-type region surrounding and spatially separated from the n-well region.

Claim 19

The electrostatic protection circuit of claim 16 wherein the first and second p-type regions are doped to p+ doping levels.

Claim 20

The electrostatic protection circuit of claim 17 wherein the n-type region is doped to an n+ doping level.

Claim 21

An electrostatic discharge protection circuit which forms part of an integrated circuit having a VDD line and a VSS line, said protection circuit comprising: an ESD transient detection circuit connected between the VDD and VSS lines; and an electrostatic discharge circuit electrically coupled to said transient detection circuit and connected between said VDD and VSS lines, wherein said discharge circuit comprises a bipolar transistor having an emitter and a collector, one of which is electrically connected to the VDD line and the other of which is electrically connected to the VSS line, wherein said bipolar transistor is implemented by a vertical bipolar transistor, wherein said vertical bipolar transistor is a n-p-n device; and wherein said electrostatic discharge circuit is formed in a n-type substrate and said vertical bipolar transistor comprises: a p-well region extending into said n-type substrate; a p-type region extending into said p-well region; a first n-type region extending into said p-well region, said first n-type region surrounding and spatially separated from the p-type region and forming an emitter of said vertical bipolar transistor; and a second n-type region extending into said n-type substrate, said second n-type region surrounding and spatially separated from the p-well region.

Claim 22

An electrostatic discharge protection circuit which forms part of an integrated circuit having a VDD line and a VSS line, said protection circuit comprising: an ESD transient detection circuit connected between the VDD and VSS lines; and an electrostatic discharge circuit electrically coupled to said transient detection circuit and connected between said VDD and VSS lines, wherein said discharge circuit comprises a bipolar transistor having an emitter and a collector, one of which is electrically connected to the VDD line and the other of which is electrically connected to the VSS line, wherein said bipolar transistor is implemented by a vertical bipolar transistor, wherein said vertical bipolar transistor is a n-p-n device; and wherein said electrostatic discharge circuit is formed in a n-type substrate and said vertical bipolar transistor comprises: a p-well region extending into said n-type substrate; a p-type region extending into said p-well region; a first n-type region extending into said p-well region, said first n-type region surrounding and spatially separated from the p-type region and forming an emitter of said vertical bipolar transistor; and a second n-type region extending into said n-type substrate, said second n-type region surrounding and spatially separated from the p-well region.

Claim 23

The electrostatic protection circuit of claim 19 wherein the first and second n-type regions are doped to n+ doping levels.

Claim 24

The electrostatic protection circuit of claim 20 wherein the p-type region is doped to a p+ doping level.

Claim 25

An electrostatic discharge protection circuit which forms part of an integrated circuit having a VDD line and a VSS line, said protection circuit comprising: an ESD transient detection circuit connected between the VDD and VSS lines wherein said ESD transient detection circuit comprises a resistor in series with a capacitor and an inverter coupled to the resistor and capacitor; and an electrostatic discharge circuit electrically coupled to said transient detection circuit and connected between said VDD and VSS lines, wherein said discharge circuit comprises a bipolar transistor having an emitter and a collector, one of which is electrically connected to the VDD line and the other of which is electrically connected to the VSS line, wherein said bipolar transistor is implemented by a structure selected from a group consisting of a vertical bipolar transistor and a field oxide device, and wherein said bipolar transistor has a base that is electrically coupled to the transient detection circuit.

Claim 26

An electrostatic discharge protection circuit which forms part of an integrated circuit having a VDD line and a VSS line, said protection circuit comprising: an ESD transient detection circuit connected between the VDD and VSS lines wherein said ESD transient detection circuit comprises a resistor in series with a capacitor and an inverter coupled to the resistor and capacitor; and an electrostatic discharge circuit electrically coupled to said transient detection circuit and connected between said VDD and VSS lines, wherein said discharge circuit comprises a bipolar transistor having an emitter and a collector, one of which is electrically connected to the VDD line and the other of which is electrically connected to the VSS line, wherein said bipolar transistor is implemented by a structure selected from a group consisting of a vertical bipolar transistor and a field oxide device, and wherein said bipolar transistor has a base that is electrically coupled to the transient detection circuit.

Claim 27

The electrostatic protection circuit of claim 22 wherein the capacitor is implemented by a NMOS device.

Claim 28

The electrostatic protection circuit of claim 23 wherein the inverter comprises a PMOS device and an NMOS device connected in series.

Claim 29

The electrostatic protection circuit of claim 24 wherein the output of the inverter drives the base of the bipolar transistor.