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US5742557A
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Multi-port random access memory
Assignee: Nortel Networks Ltd
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Filing: 1996-09-19
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Granted: 1998-04-21
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Expires: 2016-09-19
Abstract
Abstract Disclosed is an architecture of a RAM (random access memory) with BIST (built-in self test) or functional test function. The RAM has a memory cell for storing differential or single-ended binary data and bit line signals are fully differential or single-ended. Shadow write is applied to read only and read-write bit lines. With the test function, port-to-port bit line shorts and port-to-port word line shorts are sensitized.
Inventors
- 👤 Robert George Gibbins
- 👤 Garnet Frederick Randall Gibson
- 👤 Steven William Wood
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:53
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/02; G11C29/04; G11C29/50; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
161 words
A multi-port RAM comprising RAM cells of m rows by n columns, each RAM cell including storage means for storing differential binary data, the RAM cells of each column being commonly coupled to a respective set of M data paths, m, n and M being integers, the multi-port RAM further comprising: access means for conducting data access to the RAM cells via the data paths; path select means for determining data paths so that data accessing is enabled via selected data paths and data accessing is disabled via non-selected data paths, the path select means comprising N groups of M switching means coupled to the respective M data paths, N being an integer; means for selectively applying a control signal to one or more groups of M switching means; and means for activating the M switching means of the group in response to the applied control signal, each activated switching means setting the respective data path to a predetermined voltage level.
Claim 2
Dependent Claim
161 words
A multi-port RAM comprising RAM cells of m rows by n columns, each RAM cell including storage means for storing differential binary data, the RAM cells of each column being commonly coupled to a respective set of M data paths, m, n and M being integers, the multi-port RAM further comprising: access means for conducting data access to the RAM cells via the data paths; path select means for determining data paths so that data accessing is enabled via selected data paths and data accessing is disabled via non-selected data paths, the path select means comprising N groups of M switching means coupled to the respective M data paths, N being an integer; means for selectively applying a control signal to one or more groups of M switching means; and means for activating the M switching means of the group in response to the applied control signal, each activated switching means setting the respective data path to a predetermined voltage level.
Claim 3
Dependent Claim
42 words
The multi-port RAM of claim 1, wherein the path select means comprises two groups of M switching means and the means for selectively applying a control signal comprises means for alternately applying the control signal to one group of M switching means.
Claim 4
Dependent Claim
134 words
A multi-port RAM comprising RAM cells of m rows by n columns, each RAM cell including storage means for storing differential binary data, the RAM cells of each column being commonly coupled to a respective set of M data paths, m, n and M being integers, the multi-port RAM further comprising: path select means for determining data paths so that data accessing is enabled via the selected data paths and data accessing is disabled via the non-selected data paths; data read means for reading differential binary data stored in the storage means of the RAM cell via the selected data path in a read mode; and test means for determining whether or not the differential binary data read by the data read means from the storage means of the RAM cell is expected data.
Claim 5
Dependent Claim
134 words
A multi-port RAM comprising RAM cells of m rows by n columns, each RAM cell including storage means for storing differential binary data, the RAM cells of each column being commonly coupled to a respective set of M data paths, m, n and M being integers, the multi-port RAM further comprising: path select means for determining data paths so that data accessing is enabled via the selected data paths and data accessing is disabled via the non-selected data paths; data read means for reading differential binary data stored in the storage means of the RAM cell via the selected data path in a read mode; and test means for determining whether or not the differential binary data read by the data read means from the storage means of the RAM cell is expected data.
Claim 6
Dependent Claim
160 words
A multi-port RAM comprising RAM cells of m rows by n columns, each RAM cell including storage means for storing differential binary data, the RAM cells of each column being commonly coupled to a respective set of M data paths, m, n and M being integers, the multi-port RAM further comprising: path select means for determining data paths so that data accessing is enabled via the selected data paths and data accessing is disabled via the non-selected data paths; data write means for storing differential binary data in the storage means of the RAM cell via the selected data path in a write mode: data read means for reading the differential binary data stored in the storage means of the RAM cell via the selected data path in a read mode; and test means for determining whether or not the differential binary data read by the data read means from the storage means of the RAM cell is expected data.
Claim 7
Dependent Claim
160 words
A multi-port RAM comprising RAM cells of m rows by n columns, each RAM cell including storage means for storing differential binary data, the RAM cells of each column being commonly coupled to a respective set of M data paths, m, n and M being integers, the multi-port RAM further comprising: path select means for determining data paths so that data accessing is enabled via the selected data paths and data accessing is disabled via the non-selected data paths; data write means for storing differential binary data in the storage means of the RAM cell via the selected data path in a write mode: data read means for reading the differential binary data stored in the storage means of the RAM cell via the selected data path in a read mode; and test means for determining whether or not the differential binary data read by the data read means from the storage means of the RAM cell is expected data.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-04-20 | 2001-10-20 | 2002-04-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-04-20 | 2005-10-20 | 2006-04-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-04-20 | 2009-10-20 | 2010-04-21 | $7700.00 | Window Closed / Lapsed |