Semiconductor test system linked to cad data

Claim 1

A semiconductor test system for testing a semiconductor device by applying test signals to the semiconductor device under test for each reference clock period and comparing the resulting output signal from the device under test with expected data, comprising: means for extracting, from CAD design data for the semiconductor device under test, design information on predetermined terminals of a semiconductor device under test and waveform changes in a test vector to be applied to the semiconductor device under test, said extracting means including means for converting time data in said CAD design data with respect to said waveform changes which is asynchronous with said reference clock period of said semiconductor test system to delay time data expressed relative to said reference clock period; an event memory for storing event data indicating existence of said waveform changes within said reference clock period in the test vector extracted from said CAD design data with respect to the data indicating the terminals of said semiconductor device under test; a delay data memory for storing said delay time data from said extracting means indicating the time delay of said waveform changes expressed as time differences from said reference clock period; a waveform data memory for storing waveform data indicating a type of waveform with respect to each of said waveform changes; means for providing address signals to each of the memories at said reference clock period; and a time delay circuit for adding the delay time to an output signal read out from the event memory at said reference clock period, based on the delay time data read out from the delay data memory.