Wave shaping transmit circuit

Claim 2

A driver circuit for driving a data signal onto a communication channel, characterized in that said driver circuit comprises: a first output buffer including a multiplicity of pull-up transistors and a multiplicity of pull-down transistors coupled to a first output conductor through pull-up resistors and pull-down resistors, respectively; a multiplicity of delay circuits supplying a plurality of delayed data signals to the control terminals of the pull-up and pull-down transistors; and control circuitry for selectively activating the delay circuits in accordance with the data input signal.

Claim 3

The driver circuit of claim 1 wherein said control circuitry comprises multiplexers each having an output that is coupled to the input of a corresponding delay circuit.

Claim 4

The driver circuit of any one of the preceding claims wherein said driver circuit further comprises a second output buffer including a multiplicity of pull-up transistors and a multiplicity of pull-down transistors coupled to a second output conductor through pull-up resistors and pull-down resistors, respectively; and still further comprises inverters for supplying inverted data signals from said delay circuits to the control terminals of the transistors in said second output buffer.

Claim 5

The driver circuit of claim 1 or 2 wherein said pull-up and pull-down resistors have nominally equal values, whereby a constant output impedance driver circuit is obtained.

Claim 6

The driver circuit of claim 3 wherein said pull-up and pull-down resistors have nominally equal values, whereby a constant output impedance driver circuit is obtained.

Claim 7

The driver circuit of claim 1 wherein the first output buffer, the multiplicity of delay circuits and the control circuitry are fabricated together on an integrated circuit.

Claim 8

The driver circuit of claim 1 wherein the first output buffer operates to provide a constant impedance voltage source with slew rate-limiting.

Claim 9

The driver circuit of claim 6 wherein the first output buffer operates to provide a constant impedance voltage source with slew rate-limiting so that the driver circuit can be directly interfaced with the communication channel without requiring an external low-pass filter.

Claim 10

A data transmitter comprising an integrated circuit that includes a driver circuit for receiving a data signal and for driving the data signal onto a communication channel, characterized in that said driver circuit comprises; a first output buffer coupled to a first output conductor and a second output buffer coupled to a second output conductor, with each buffer including a multiplicity of pull-up transistors and a multiplicity of pull-down transistors coupled to the associated output conductor through pull-up resistors and pull-down resistors, respectively; a multiplicity of delay circuits supplying a plurality of delayed data signals to the control terminals of the pull-up and pull-down transistors; and control circuitry for selectively activating the delay circuits; and wherein said data transmitter further comprises a center-tapped transformer having first and second output conductors respectively, and having first and second output terminals for connection to twisted pair cable.

Claim 11

A data transmitter comprising an integrated circuit that includes a driver circuit for receiving a data signal and for driving the data signal onto a communication channel, characterized in that said driver circuit comprises; a first output buffer coupled to a first output conductor and a second output buffer coupled to a second output conductor, with each buffer including a multiplicity of pull-up transistors and a multiplicity of pull-down transistors coupled to the associated output conductor through pull-up resistors and pull-down resistors, respectively; a multiplicity of delay circuits supplying a plurality of delayed data signals to the control terminals of the pull-up and pull-down transistors; and control circuitry for selectively activating the delay circuits; and wherein said data transmitter further comprises a center-tapped transformer having first and second output conductors respectively, and having first and second output terminals for connection to twisted pair cable.

Claim 12

The data transmitter of claim 9 wherein said control circuitry comprises multiplexers each having an output that is coupled to the input of a corresponding delay circuit.

Claim 13

A data communication system comprising a communication channel and a data transmitter comprising an integrated circuit that includes a driver circuit for receiving a data signal from an input node and for driving the data signal onto said communication channel, characterized in that said driver circuit comprises: a first output buffer coupled to a first output conductor and a second output buffer coupled to a second output conductor, with each buffer including a multiplicity of pull-up transistors and a multiplicity of pull-down transistors coupled to the associated output conductor through pull-up resistors and pull-down resistors, respectively; a multiplicity of delay circuits coupled to said input node and supplying a plurality of delayed data signals to the control terminals of the pull-up and pull-down transistors; and control circuitry for selectively activating the delay circuits.

Claim 14

A data communication system comprising a communication channel and a data transmitter comprising an integrated circuit that includes a driver circuit for receiving a data signal from an input node and for driving the data signal onto said communication channel, characterized in that said driver circuit comprises: a first output buffer coupled to a first output conductor and a second output buffer coupled to a second output conductor, with each buffer including a multiplicity of pull-up transistors and a multiplicity of pull-down transistors coupled to the associated output conductor through pull-up resistors and pull-down resistors, respectively; a multiplicity of delay circuits coupled to said input node and supplying a plurality of delayed data signals to the control terminals of the pull-up and pull-down transistors; and control circuitry for selectively activating the delay circuits.

Claim 15

The system of claim 11 wherein said communication channel comprises a twisted-pair cable, and wherein said data transmitter further comprises a center-tapped transformer having first and second input terminals coupled to said first and second output conductors respectively, and having first and second output terminals coupled to said twisted pair cable.

Claim 16

The system of claim 11 or claim 12 wherein said control circuitry comprises multiplexers each having an output that is coupled to the input of a corresponding delay circuit.

Claim 17

The system of claim 13 wherein at least one of said multiplexers has a first input coupled to the output of a proceeding delay circuit, and having a second input coupled to the output of a succeeding delay circuit.

Claim 20

The method of claim 15 wherein said control circuitry comprises multiplexers each having an output that is coupled to the input of a corresponding delay circuit.

Claim 21

The method of claim 15 or 16 wherein said driver circuit further comprises a second output buffer including a multiplicity of pull-up transistors and a multiplicity of pull-down transistors coupled to a second output conductor through pull-up resistors and pull-down resistors, respectively; and still further comprises inverters for supplying inverted data signals from said delay circuits to the control terminals of the transistors in said second output buffer.

Claim 23

The method of claim 15 further comprising the step of: providing a step-wise voltage transition to the communication channel to effect a smoothing of a voltage output seen by the communication channel.

Claim 24

A driver circuit for driving a data signal onto a communication channel, characterized in that said driver circuit comprises: a first output buffer including a multiplicity of pull-up transistors and a multiplicity of pull-down resistors, respectively; a multiplicity of delay circuits supplying a plurality of delayed data signals to the control terminals of the pull-up and pull-down transistors; and control circuitry for selectively activating the delay circuits in accordance with said data signal, said control circuitry comprising multiplexers each having an output that is coupled to the input of a corresponding delay circuit, wherein at least one of said multiplexers has a first input coupled to the output of a preceding delay circuit, and having a second input coupled to the output of a succeeding delay circuit.

Claim 25

A driver circuit for driving a data signal onto a communication channel, characterized in that said driver circuit comprises: a first output buffer including a multiplicity of pull-up transistors and a multiplicity of pull-down resistors, respectively; a multiplicity of delay circuits supplying a plurality of delayed data signals to the control terminals of the pull-up and pull-down transistors; and control circuitry for selectively activating the delay circuits in accordance with said data signal, said control circuitry comprising multiplexers each having an output that is coupled to the input of a corresponding delay circuit, wherein at least one of said multiplexers has a first input coupled to the output of a preceding delay circuit, and having a second input coupled to the output of a succeeding delay circuit.

Claim 26

A data transmitter comprising an integrated circuit that includes a driver circuit for receiving a data signal and for driving the data signal onto a communication channel, characterized in that said driver circuit comprises a first output buffer coupled to a first output conductor and a second output buffer coupled to a second output conductor, with each buffer including a multiplicity of pull-up transistors and a multiplicity of pull-down transistors coupled to the associated output conductor through pull-up resistors and pull-down resistors, respectively; a multiplicity of delay circuits supplying a plurality of delayed data signals to the control terminals of the pull-up and pull-down transistors; and control circuitry for selectively activating the delay circuits, said control circuitry comprising multiplexers each having an output that is coupled to the input of a corresponding delay circuit, wherein at least one of said multiplexers has a first input coupled to the output of a preceding delay circuit, and having a second input coupled to the output of a succeeding delay circuit; and wherein said data transmitter further comprises a center-tapped transformer having first and second input terminals coupled to said first and second output conductors respectively, and having first and second output terminals for connection to twisted pair cable.

Claim 27

A data transmitter comprising an integrated circuit that includes a driver circuit for receiving a data signal and for driving the data signal onto a communication channel, characterized in that said driver circuit comprises a first output buffer coupled to a first output conductor and a second output buffer coupled to a second output conductor, with each buffer including a multiplicity of pull-up transistors and a multiplicity of pull-down transistors coupled to the associated output conductor through pull-up resistors and pull-down resistors, respectively; a multiplicity of delay circuits supplying a plurality of delayed data signals to the control terminals of the pull-up and pull-down transistors; and control circuitry for selectively activating the delay circuits, said control circuitry comprising multiplexers each having an output that is coupled to the input of a corresponding delay circuit, wherein at least one of said multiplexers has a first input coupled to the output of a preceding delay circuit, and having a second input coupled to the output of a succeeding delay circuit; and wherein said data transmitter further comprises a center-tapped transformer having first and second input terminals coupled to said first and second output conductors respectively, and having first and second output terminals for connection to twisted pair cable.