EP0452684A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A reduced noise, data output stage of the buffer type for logic circuits of the CMOS type
Assignee: STMicroelectronics SRL
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Filing: 1991-03-19
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Granted: —
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Expires: 2011-03-19
Abstract
Abstract A reduced noise, data output stage (1) of the buffer type, intended for CMOS logic circuits, comprises pairs (5,6,7) of transistors (M1,M4,M2,M5,M3,M6) connected in parallel with one another between a pair of inputs (2,3) and a data output (4). These transistor pairs (5,6,7) are driven through respective resistive control lines including respective resistors (R1,R2) which are connected between corresponding gate electrodes of the first and the second transistor pairs, and of the second and the third transistor pairs, to reduce the value of the differential ratio dI/dt, while also reducing switching noise.
Inventors
- 👤 Marco Dallabora
- 👤 Paolo Rolandi
- 👤 Marco Maccalli
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 02:54
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
56 words
A reduced noise, data output stage (1) of the buffer type for CMOS logic circuits, being of the type which comprises transistor (M1,M4,M2,M5,M3,M7) pairs (5,6,7) connected in parallel to one another between a pair of inputs (2,3) and a data output (4), characterized in that said transistor pairs (5,6,7) are driven through respective resistive control lines.
Claim 2
Dependent Claim
23 words
An output stage according to Claim 1, characterized in that said control lines comprise respective resistors (R1,R2) connected between each transistor pair (5,6,7).
Claim 3
Dependent Claim
18 words
An output stage according to Claim 1, characterized in that it comprises three pairs of n-channel MOS transistors.
Claim 4
Dependent Claim
27 words
An output stage according to Claim 3, characterized in that said pairs of MOS transistors have increasing dimensions from the first thereof connected to said inputs (2,3).
Claim 5
Dependent Claim
41 words
An output stage according to Claim 4, characterized in that it comprises respective resistors (R1,R2) connected between the corresponding gate electrodes (G1,G2,G4,G5) of the first (5) and second (6) pairs, and of the second (6) and third (7) pairs of transistors.
References Cited (Backward Citations)
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