EP0261528A1
Expired / Lapsed
EP
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A logic circuit
Assignee: Toshiba Corp
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Filing: 1987-09-11
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Granted: —
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Expires: 2007-09-11
Abstract
Abstract A logic circuit comprises a t least one signal input terminal (11), an output terminal (12), an output circuit (13) including a first bipolar transistor (15) coupled between the output terminal (12) and a reference potential terminal, to discharge the output terminal (12), and an MOS type logic circuit (16) for supplying to the base of the first bipolar transistor (15) a signal of a level corresponding to an input signal (Vin) supplied to the at least one signal input terminal (11). The logic circuit (16) further comprises a control MOS transistor (20) coupled between a power source terminal (V DD ) and the base of the bipolar transistor (15), for supplying part of the base current to the bipolar transistor (15) in response to a signal at the output terminal (12).
Inventors
- 👤 Fujio C/O Patent Division Masuoka
- 👤 Kiyofumi C/O Patent Division Ochii
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 18:12
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/013; H03K19/0136; H03K19/0008; H03K19/001; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
127 words
A logic circuit comprising: at least one signal input terminal (Vin; Vin1, Vin2); an output terminal (Vout); output circuit means (13) including a first bipolar transistor (15) coupled between the outp ut terminal (Vout) and a reference potential terminal, to discharge said output terminal (Vout); MOS logic circuit means (16) for supplying to the base of said first bipolar transistor a signal of a level corresponding to an input signal supplied to said at least one signal input terminal (Vin; Vin1, Vin2); and a control MOS transistor (20) coupled between a power source terminal (V DD ) and the base of said bipolar transistor (15), and for supplying part of base current to the bipolar transistor (15) in response to the signal at said output terminal (Vout).
Claim 2
Dependent Claim
127 words
A logic circuit comprising: at least one signal input terminal (Vin; Vin1, Vin2); an output terminal (Vout); output circuit means (13) including a first bipolar transistor (15) coupled between the outp ut terminal (Vout) and a reference potential terminal, to discharge said output terminal (Vout); MOS logic circuit means (16) for supplying to the base of said first bipolar transistor a signal of a level corresponding to an input signal supplied to said at least one signal input terminal (Vin; Vin1, Vin2); and a control MOS transistor (20) coupled between a power source terminal (V DD ) and the base of said bipolar transistor (15), and for supplying part of base current to the bipolar transistor (15) in response to the signal at said output terminal (Vout).
Claim 3
Dependent Claim
93 words
The logic circuit according to claim 1, characterized in that said output circuit means (13) further includes a second bipolar transistor (14) coupled between said power source terminal (V DD ) and the output terminal (Vout), said logic circuit means (16) includes a first MOS transistor (17) of one channel type coupled between said power source terminal (V DD ) and the base of the second bipolar transistor (14), and a second MOS transistor (18) of an opposite channel type coupled between said control MOS transistor (20) and the first bipolar transistor (15).
Claim 4
Dependent Claim
32 words
The logic circuit according to claim 2, characterized in that said logic circuit means (16) further includes a capacitor (CX) coupled between said second MOS transistor (18) and the reference potential terminal.
Claim 5
Dependent Claim
47 words
The logical circuit according to claim 2, characterized in that said circuit means (16) further includes a third MOS transistor (19) coupled between said output terminal (Vout) and the second MOS transistor (18), and whose conductivity is controlled by a signal at said signal input terminal (Vin).
Claim 6
Dependent Claim
43 words
The logic circuit according to claim 4, characterized in that said logic circuit means (16) includes first and second resistor means (38 and 37) which are respectively coupled between the bases and emitters of said first and second bipolar transistors (15 and 14).
Claim 7
Dependent Claim
55 words
The logic circuit according to claim 4, characterized in that said logic circuit means (16) further includes fourth and fifth MOS transistors (40 and 39) respectively coupled between the bases and emitters of said first and second bipolar transistors (15 and 14), and whose gates are coupled with said power source terminal (V DD ).
Claim 8
Dependent Claim
75 words
The logic circuit according to claim 4, characterized in that said logic circuit means (16) further includes a fourth MOS transistor (40) coupled between the base and emitter of the first bipolar transistor, and whose gate is coupled with the output terminal (Vout), and a fifth MOS transistor (39) coupled between the base of the second bipolar transistor (14) and the reference potential terminal, and whose gate is coupled with the signal input terminal (Vin).
Claim 9
Dependent Claim
76 words
The logic circuit according to claim 4, characterized in that said logic circuit means (16) further includes a fourth MOS transistor (40) coupled between the base and emitter of the first bipolar transistor, and whose gate is coupled with the first MOS transistor (17), and a fifth MOS transistor (39) coupled between the base of the second bipolar transistor (14) and the reference potential terminal, and whose gate is coupled with the signal input terminal (Vin).
Claim 10
Dependent Claim
77 words
The logic circuit according to claim 4, characterized in that said logic circuit means (16) further includes a fourth MOS transistor (40) coupled between the base and emitter of the first bipolar transistor, and whose gate is coupled with the first MOS transistor (17), and a fifth MOS transistor (39) coupled between the base of the second bipolar transistor (14) and the second MOS transistor (18), and whose gate is coupled with the signal input terminal (Vin).
Claim 11
Dependent Claim
82 words
The logic circuit according to claim 1, characterized in that a plurality of said signal input terminals (Vin1, Vin2) are provided, said output circuit means (13) further includes a second bipolar transist or (14) coupled between the power source terminal (V DD ) and output terminal (Vout), and said logic circuit means (16) supplies to the bases of said first and second bipolar transistors (15 and 14) signals of levels corresponding to signals at said plurality of signal input terminals (Vin1, Vin2).
Claim 12
Dependent Claim
138 words
The logic circuit according to claim 10, characterized in that said logic circuit means (16) includes first MOS transistors (17A, 18B) of one channel type coupled in parallel between the power source terminal (V DD ) and the base of second bipolar transistor (14), and whose gates are respectively coupled with the plurality of signal input terminals (Vin1, Vin2), second MOS transistors (18A, 18B) of an opposite channel type coupled in series between the base of the first bipolar transistor (15) and said control MOS transistor (20) and whose gates are respectively coupled with the plurality of said input terminals, third MOS transistors (19A, 19B) of the opposite channel type coupled in series between the output terminal (V DD ) and control MOS transistor (20), and whose gates are respectively coupled with the plurality of said input terminals.
Claim 13
Dependent Claim
137 words
The logic circuit according to claim 10, characterized in that said logic circuit means (16) includes first MOS transistors (17A, 18B) of one channel type coupled in series between the power source terminal (V DD ) and the base of second bipolar transistor (14), and whose gates are respectively coupled with the plurality of signal input terminals (Vin1, Vin2), second MOS transistors (18A, 18B) of an opposite channel type coupled in series between the base of the first bipolar transistor (15) and control MOS transistor (20) and whose gates are respectively coupled with the plurality of said input terminals, third MOS transistors (19A, 19B) of the opposite channel type coupled in parallel between the output terminal (V DD ) and control MOS transistor (20), and whose gates are respectively coupled with the plurality of said input terminals.
Claim 14
Dependent Claim
57 words
The logic circuit according to claim 11 or 12, characterized in that said logic circuit means (16) further includes an MOS transistor (40) of the opposite channel type coupled between the base of the first bipolar transistor (15) and the reference potential terminal, and whose gate is coupled with the base of the second bipolar transistor (14).
Claim 15
Dependent Claim
56 words
The logic circuit according to claim 11, characterized in that said logic circuit means(16) further includes MOS transistors (39A, 39B) of the opposite type coupled in series between the base of the second bipolar transistor (14) and the reference potential terminal, and whose gates are respectively coupled with the plurality of signal input terminals (Vin1, Vin2).
Claim 16
Dependent Claim
55 words
The logic circuit according to claim 11, characterized in that said logic circuit means (16) further includes MOS transistors (39A, 39B) of the opposite type coupled in series between the base of the first and second bipolar transistors (14, 15), and whose gates are respectively coupled with the plurality of signal input terminals (Vin1, Vin2).
Claim 17
Dependent Claim
57 words
The logic circuit according to claim 12, characterized in that said logic circuit means (16) further includes MOS transistors (39A, 39B) of the opposite type coupled in parallel between the base of the second bipolar transistor (14) and the reference potential terminal, and whose gates are respectively coupled with the plurality of signal input terminals (Vin1, Vin2).
Claim 18
Dependent Claim
56 words
The logic circuit according to claim 12, characterized in that said logic circuit means (16) further includes an MOS transistor of the opposite channel type coupled in parallel between the bases of the first and second bipolar transistors (15 and 14), and whose gates are respectively coupled with the plurality of signal input terminals (Vin1, Vin2).
References Cited (Backward Citations)
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