Patent US5737631A successfully refreshed from Google Patents.
US5737631A
Expired / Lapsed
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Reprogrammable instruction set accelerator
Assignee: Xilinx Inc
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Filing: 1995-04-05
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Granted: 1998-04-07
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Expires: 2015-04-05
Abstract
Abstract A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined set of instructions, combined with a programmable execution unit coupled to the internal buses for execution of a programmed instruction providing an on chip reprogrammable instruction set accelerator RISA. The programmable execution unit may be made using a field programmable gate array having a configuration store, and resources for accessing the configuration store to program the programmable execution unit. An instruction register is included in the data processor which holds a current instruction for execution, and is coupled to an instruction data path to supply the instruction to the defined instruction unit and to the programmable instruction unit in parallel, through appropriate decoding resources. A condition code register is coupled to instruction fetching resources, and connected to receive condition codes from both the defined execution unit and from the programmable execution unit. The programmable execution unit includes logic to signal the instruction fetching resources to provide a next instruction when execution of the programmed instruction is done. Resources for accessing the configuration store to program the programmable execution unit are provided, which can utilize the internal buses of the data processor or be completely independent of them.
Inventors
- 👤 Stephen M. Trimberger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 01:16
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F15/00; G06F15/76; G06F15/78; G06F15/7867; G06F8/00; G06F8/40; G06F8/41; G06F8/44; G06F8/447; G06F9/30094; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/30181; G06F9/3877; G06F9/3885; G06F9/3893; G06F9/3895; G06F9/3897
Claims Analysis
Total Claims: 44
Claim 1
Independent Claim
60 words
A data processor comprising: internal buses for operand and result data; a defined execution unit coupled to the internal buses for execution of defined instructions; a programmable execution unit coupled to the internal buses for execution of a programmed instruction; and a condition code register connected to the programmable execution unit to receive condition codes from the programmable execution unit.
Claim 2
Dependent Claim
60 words
A data processor comprising: internal buses for operand and result data; a defined execution unit coupled to the internal buses for execution of defined instructions; a programmable execution unit coupled to the internal buses for execution of a programmed instruction; and a condition code register connected to the programmable execution unit to receive condition codes from the programmable execution unit.
Claim 3
Dependent Claim
58 words
The data processor of claim 1, wherein at least one internal bus is divided into a first section and a second section, wherein the first section is coupled to the defined execution unit and not the programmable execution unit, and wherein the second section is coupled to the programmable execution unit and not the defined execution execution unit.
Claim 4
Dependent Claim
45 words
The data processor of claim 1, wherein at least one internal bus is divided into two sections, thereby allowing the defined execution unit and the programmable execution unit to share input signals and yet provide independent output signals to the at least one internal bus.
Claim 5
Dependent Claim
38 words
The data processor of claim 1, wherein the internal buses include a first bus and a second bus, and the defined execution unit and the programmable execution unit are connected in parallel across the first and second buses.
Claim 6
Dependent Claim
17 words
The data processor of claim 1, wherein the programmable execution unit comprises a field programmable gate array.
Claim 7
Dependent Claim
48 words
The data processor of claim 1, including: an instruction register which holds a current instruction for execution, and an instruction data path supplying the instruction to the defined execution unit and to the programmable execution unit, wherein each said instruction is characterized by a plurality of instruction fields.
Claim 8
Dependent Claim
14 words
The data processor of claim 6, wherein the instruction data path includes a decoder.
Claim 9
Dependent Claim
29 words
The data processor of claim 6, wherein the instructions have a prespecified format, including an opcode field specifying an operation by one of the defined and programmable execution units.
Claim 10
Dependent Claim
21 words
The data processor of claim 8, wherein the prespecified format includes a defined/programmed flag, specifying a defined or a programmed instruction.
Claim 11
Dependent Claim
40 words
The data processor of claim 8, wherein the prespecified format includes an immediate data field, and programmed instructions use the immediate data field to identify a programmed operation and the opcode field to identify the instruction as a programmed instruction.
Claim 12
Dependent Claim
42 words
The data processor of claim 6, wherein the instructions have a prespecified format, including a defined opcode field for specifying an operation by the defined execution unit, and a programmed opcode field for specifying a programmed operation by the programmable execution unit.
Claim 13
Dependent Claim
19 words
The data processor of claim 6, wherein all fields of the instructions are provided to the programmable execution unit.
Claim 14
Dependent Claim
43 words
The data processor of claim 1, including: an instruction fetching resources responsive to condition codes; and a condition code register, coupled with the instruction fetching resources, and connected to receive condition codes from the defined execution unit and from the programmable execution unit.
Claim 15
Dependent Claim
32 words
The data processor of claim 1, including: an instruction state machine; and the programmable execution unit includes logic to signal the instruction state machine when execution of a programmed instruction is done.
Claim 16
Dependent Claim
18 words
The data processor of claim 1, wherein the programmable execution unit receives programming information through the internal buses.
Claim 17
Dependent Claim
23 words
The data processor of claim 1, wherein the programmable execution unit receives programming information through a configuration port independent of the internal buses.
Claim 18
Dependent Claim
18 words
The data processor of claim 1, including: logic which indicates that the programmable execution unit is being configured.
Claim 19
Dependent Claim
27 words
The data processor of claim 1, including: a register file, coupled to the internal buses, accessible by both the defined execution unit and the programmable execution unit.
Claim 20
Dependent Claim
19 words
The data processor of claim 1, including a set of registers dedicated for use by the defined execution unit.
Claim 21
Dependent Claim
19 words
The data processor of claim 1, including a set of registers dedicated for use by the programmable execution unit.
Claim 22
Dependent Claim
16 words
The data processor of claim 1, including a data port coupled to the programmable execution unit.
Claim 23
Dependent Claim
26 words
The data processor of claim 21, wherein the data port comprises a source of operand data for the programmable execution unit, independent of the internal buses.
Claim 24
Dependent Claim
26 words
The data processor of claim 21, wherein the data port comprises a destination of operand data for the programmable execution unit, independent of the internal buses.
Claim 25
Dependent Claim
133 words
A microprocessor, comprising: internal buses for operand and result data; a defined execution unit coupled to the internal buses for execution of defined instructions; a programmable execution unit coupled to the internal buses for execution of a programmed instruction; resources for accessing the programmable execution unit to define programmed instructions; an instruction register which holds a current instruction for execution, and an instruction data path from the instruction register, including a decoder supplying control signals in response to instructions to the defined execution unit and to the programmable execution unit; an instruction state machine, responsive to condition codes, which supply instructions to the instruction register; and a condition code register, coupled with the instruction fetching resources, and connected to receive condition codes from the defined execution unit and from the programmable execution unit.
Claim 26
Dependent Claim
133 words
A microprocessor, comprising: internal buses for operand and result data; a defined execution unit coupled to the internal buses for execution of defined instructions; a programmable execution unit coupled to the internal buses for execution of a programmed instruction; resources for accessing the programmable execution unit to define programmed instructions; an instruction register which holds a current instruction for execution, and an instruction data path from the instruction register, including a decoder supplying control signals in response to instructions to the defined execution unit and to the programmable execution unit; an instruction state machine, responsive to condition codes, which supply instructions to the instruction register; and a condition code register, coupled with the instruction fetching resources, and connected to receive condition codes from the defined execution unit and from the programmable execution unit.
Claim 27
Dependent Claim
47 words
The microprocessor of claim 24, wherein the programmable execution unit comprises field programmable gate array logic having a configuration store, and the resources for accessing the programmable execution unit include a data path to the configuration store to program the programmable execution unit through the internal buses.
Claim 28
Dependent Claim
49 words
The microprocessor of claim 24, wherein the programmable execution unit comprises field programmable gate array logic having a configuration store, and the resources for accessing the programmable execution unit include a configuration port independent of the internal buses for accessing the configuration store to program the programmable execution unit.
Claim 29
Dependent Claim
26 words
The microprocessor of claim 24, wherein: the programmable execution unit includes logic to signal the instruction state machine when execution of a programmed instruction is done.
Claim 30
Dependent Claim
28 words
The microprocessor of claim 24, wherein the instructions have a prespecified format, including an opcode field specifying an operation by one of the defined and programmable execution units.
Claim 31
Dependent Claim
20 words
The microprocessor of claim 28, wherein the prespecified format includes a defined/programmed flag, specifying a defined or a programmed instruction.
Claim 32
Dependent Claim
39 words
The microprocessor of claim 28, wherein the prespecified format includes an immediate data field, and programmed instructions use the immediate data field to identify a programmed operation and the opcode field to identify the instruction as a programmed instruction.
Claim 33
Dependent Claim
41 words
The microprocessor of claim 24, wherein the instructions have a prespecified format, including a defined opcode field for specifying an operation by the defined execution unit, and a programmed opcode field for specifying a programmed operation by the programmable execution unit.
Claim 34
Dependent Claim
37 words
The microprocessor of claim 24, wherein the internal buses include a first bus and a second bus, and the defined execution unit and the programmable execution unit are connected in parallel across the first and second buses.
Claim 35
Dependent Claim
17 words
The microprocessor of claim 24, including: logic which indicates that the programmable execution unit is being configured.
Claim 36
Dependent Claim
26 words
The microprocessor of claim 24, including: a register file, coupled to the internal buses, accessible by both the defined execution unit and the programmable execution unit.
Claim 37
Dependent Claim
18 words
The microprocessor of claim 24, including a set of registers dedicated for use by the defined execution unit.
Claim 38
Dependent Claim
18 words
The microprocessor of claim 24, including a set of registers dedicated for use by the programmable execution unit.
Claim 39
Dependent Claim
31 words
The microprocessor of claim 24, including a data port coupled to the programmable execution unit comprising a source of operand data for the programmable execution unit, independent of the internal buses.
Claim 40
Dependent Claim
31 words
The microprocessor of claim 24, including a data port coupled to the programmable execution unit comprising a destination of operand data for the programmable execution unit, independent of the internal buses.
Claim 41
Dependent Claim
69 words
A data processor comprising: internal buses for operand and result data; a defined execution unit coupled to the internal buses for execution of defined instructions; a programmable execution unit coupled to the internal buses for execution of a programmed instruction; and a configuration data bus coupled to the programmable execution unit whereby the programmable execution unit is configured with data received from a source external to the data processor.
Claim 42
Dependent Claim
69 words
A data processor comprising: internal buses for operand and result data; a defined execution unit coupled to the internal buses for execution of defined instructions; a programmable execution unit coupled to the internal buses for execution of a programmed instruction; and a configuration data bus coupled to the programmable execution unit whereby the programmable execution unit is configured with data received from a source external to the data processor.
Claim 43
Dependent Claim
160 words
A microprocessor, comprising: internal buses for operand and result data; a defined execution unit coupled to the internal buses for execution of defined instructions; a programmable execution unit coupled to the internal buses for execution of a programmed instruction; resources for accessing the programmable execution unit to define programmed instructions; an instruction register which holds a current instruction for execution, and an instruction data path from the instruction register, including a decoder supplying control signals in response to instructions to the defined execution unit and to the programmable execution unit; an instruction state machine, responsive to condition codes, which supply instructions to the instruction register; a condition code register, coupled with the instruction fetching resources, and connected to receive condition codes from the defined execution unit and from the programmable execution unit; and a configuration data bus coupled to the programmable execution unit whereby the programmable execution unit is configured with data received from a source external to the microprocessor.
Claim 44
Dependent Claim
160 words
A microprocessor, comprising: internal buses for operand and result data; a defined execution unit coupled to the internal buses for execution of defined instructions; a programmable execution unit coupled to the internal buses for execution of a programmed instruction; resources for accessing the programmable execution unit to define programmed instructions; an instruction register which holds a current instruction for execution, and an instruction data path from the instruction register, including a decoder supplying control signals in response to instructions to the defined execution unit and to the programmable execution unit; an instruction state machine, responsive to condition codes, which supply instructions to the instruction register; a condition code register, coupled with the instruction fetching resources, and connected to receive condition codes from the defined execution unit and from the programmable execution unit; and a configuration data bus coupled to the programmable execution unit whereby the programmable execution unit is configured with data received from a source external to the microprocessor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-04-06 | 2001-10-06 | 2002-04-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-04-06 | 2005-10-06 | 2006-04-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-04-06 | 2009-10-06 | 2010-04-07 | $7700.00 | Window Closed / Lapsed |