Microprocessor power control in a multiprocessor computer system

Claim 2

A multiprocessing computer system comprising: a plurality of processing units, wherein each processing unit has a corresponding power down input, wherein an active signal on one of said power down inputs causes a corresponding processing unit to enter a reduced power usage state other than off, wherein at least one of the processing units includes a boot inhibit input to selectively prevent the at least one processing unit from becoming a boot system processor during system initialization; and a power down memory element having a plurality of memory locations, each memory location coupled to a corresponding power down input, wherein a power consumption of a selected processing unit varies in accordance with a value stored in a corresponding memory location.

Claim 3

The multiprocessing computer system of claim 1 wherein said power down memory element comprises a power down control register having a plurality of bits, wherein each of said bits corresponds to a desired signal state to be applied to the power down input of a corresponding one of said processing units.

Claim 4

The multiprocessing computer system of claim 2 further comprising: a multiprocessing bus coupled to each of said plurality of processing units; and an I/O bridge coupled to said multiprocessing bus, said i/O bridge incorporating said power down control register.

Claim 5

The multiprocessing computer system of claim 1 wherein said boot inhibit input is tied to said processing unit's power down input during system initialization.

Claim 6

A computer system comprising: a first central processing unit having a first power down input; a second central processing unit having a second power down input and a boot inhibit input, wherein the boot inhibit input selectively prevents the second central processing unit from becoming a boot system processor during system initialization; and a power down control register having a first bit coupled to communicate with the power down input of said first central processing unit and a second bit coupled to communicate with the power down input of the second central processing unit, wherein a reduced power usage state of the first and second central processing units is controlled by a value stored in the power down control register.

Claim 7

A computer system comprising: a first central processing unit having a first power down input; a second central processing unit having a second power down input and a boot inhibit input, wherein the boot inhibit input selectively prevents the second central processing unit from becoming a boot system processor during system initialization; and a power down control register having a first bit coupled to communicate with the power down input of said first central processing unit and a second bit coupled to communicate with the power down input of the second central processing unit, wherein a reduced power usage state of the first and second central processing units is controlled by a value stored in the power down control register.

Claim 8

The computer system of claim 5 further comprising: an additional plurality of central processing units, each having a power down input; said power down control register having an additional plurality of bits, each respectively coupled to a corresponding one of the power down inputs of said additional plurality of central processing units.

Claim 9

The computer system of claim 5 further comprising an I/O bridge device coupled to communicate with said first and second central processing units, said I/O bridge incorporating said power down register.

Claim 10

A computer system motherboard comprising: a first receptacle for receiving a first central processing unit said first receptacle including a first connection point for a first power down input of said first central processing unit; a second receptacle for receiving a second central processing unit, said second receptacle including a second connection point for a second power down input of said second central processing unit and a third connection point for receiving a boot inhibit signal; a power down control memory element for storing first and second processing unit power usage control bits; a first connection path coupled to provide a signal to said first connection point determined by said first power usage control bit; and a second connection path coupled to provide a signal to said second connection point determined by said second power usage control bit.

Claim 11

A computer system motherboard comprising: a first receptacle for receiving a first central processing unit said first receptacle including a first connection point for a first power down input of said first central processing unit; a second receptacle for receiving a second central processing unit, said second receptacle including a second connection point for a second power down input of said second central processing unit and a third connection point for receiving a boot inhibit signal; a power down control memory element for storing first and second processing unit power usage control bits; a first connection path coupled to provide a signal to said first connection point determined by said first power usage control bit; and a second connection path coupled to provide a signal to said second connection point determined by said second power usage control bit.

Claim 12

The computer system motherboard of claim 8 wherein said second and third connection points are coupled to receive a common signal during system initialization.

Claim 15

The method of claim 10 wherein said storing data step comprises the step of setting bits in a power down control register wherein each bit corresponds to the input signal to be provided to the power down input of a corresponding one of said plurality of processing units.