US5613126A
Expired / Lapsed
US
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Timer tick auto-chaining technique within a symmetrical multiprocessing system
Assignee: Advanced Micro Devices Inc
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Filing: 1994-05-31
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Granted: 1997-03-18
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Expires: 2014-05-31
Abstract
Abstract A symmetrical multiprocessing system is provided that includes centralized interrupt control unit. The interrupt control unit is coupled to a plurality of processing units and to a plurality of interrupt sources. The interrupt control unit advantageously allows for the expansion of each interrupt pin by setting the interrupt control unit in a cascade mode. Furthermore, the central control unit is responsive to specialized interrupt cycles which allows I/O devices and/or bus bridge devices to initiate of an interrupt without requiring a dedicated interrupt line. The central interrupt control unit further allows each interrupt to be prioritized independently of its associated vector ID, and prevents the occurrence of spurious interrupts by providing a programmable latency timer which causes the central interrupt control unit to delay its response to End Of Interrupt (EOI) instructions. An auto-chaining technique is further implemented by the central interrupt control unit to sequentially provide broadcast interrupts to various processing units based on their current task priority values. Finally, the central interrupt control unit further handles system management interrupts (SMIs) from sources such as power management units and ensures proper system operation even if the requested system management function affects operations being carried by other processing units.
Inventors
- 👤 Rodney Schmidt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 12:08
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/17; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
156 words
A method of broadcasting an interrupt signal from an interrupt requestor within a symmetrical multiprocessing system including a plurality of processing units comprising the steps of: receiving said interrupt signal at a central control unit; determining relative task priorities of a predetermined number of said plurality of processing units; providing from said central control unit, an interrupt corresponding to said interrupt signal to a designated one of said predetermined number of processing units having the lowest current task priority; sequentially providing from said central control unit, said interrupt signal to another of a remaining number of said predetermined number of processing units when said designated processing unit has completed service of said interrupts said another of said remaining number of said predetermined number of said processing Units having the next lowest task priority; and repeating said sequentially providing step until said interrupt signal has been provided to all of said predetermined number of said processing units.
Claim 2
Independent Claim
156 words
A method of broadcasting an interrupt signal from an interrupt requestor within a symmetrical multiprocessing system including a plurality of processing units comprising the steps of: receiving said interrupt signal at a central control unit; determining relative task priorities of a predetermined number of said plurality of processing units; providing from said central control unit, an interrupt corresponding to said interrupt signal to a designated one of said predetermined number of processing units having the lowest current task priority; sequentially providing from said central control unit, said interrupt signal to another of a remaining number of said predetermined number of processing units when said designated processing unit has completed service of said interrupts said another of said remaining number of said predetermined number of said processing Units having the next lowest task priority; and repeating said sequentially providing step until said interrupt signal has been provided to all of said predetermined number of said processing units.
Claim 3
Dependent Claim
27 words
The method as recited in claim 1 wherein the additional processing unit that is interrupted has the lowest current task priority relative to the remaining processing units.
Claim 4
Dependent Claim
38 words
The method of broadcasting an interrupt signal as recited in claim 1 wherein the step of determining the task priorities of said plurality of processing units is performed by reading a task priority register within a CPU channel.
Claim 5
Dependent Claim
31 words
The method of broadcasting an interrupt signal as recited in claim 1 wherein said designated processing unit acknowledges completion of servicing said interrupt signal by asserting an End of Interrupt command.
Claim 6
Dependent Claim
40 words
The method of broadcasting an interrupt signal as recited in claim 4 further including the steps of: determining if all of a designated group of said processors have serviced said interrupt signal; and setting said interrupt to an idle state.
Claim 7
Dependent Claim
32 words
The method of broadcasting an interrupt signal as recited in claim 5 further including the step of waiting a predetermined period of time after the receipt of said End of Interrupt command.
Claim 8
Dependent Claim
39 words
The interrupt controller of claim 6 wherein said central control unit is further capable of determining when all processing nits have received and served said interrupt signal clearing a control register indicative of an activity state of an interrupt.
Claim 9
Dependent Claim
180 words
An interrupt controller for a symmetrical multiprocessing system comprising: at least one interrupt channel configured to receive an interrupt signal; a plurality of CPU channels configured to distribute selected interrupt signals to dedicated processing units; and a central controller coupled to said at least one interrupt and to said plurality of CPU channels, wherein said central controller is configured to determine a designated processing unit of a predetermined number of processing units having a lowest task priority level and to provide said interrupt to said designated processing unit, and is configured to provide subsequently said interrupt signal to a subsequent processing unit of a remaining number of said predetermined number of said processing units having a higher associated task priority after said designated processing unit completes its service of said interrupt signal and is further configured to provide said interrupt signal to each next subsequent processing unit of said remaining number of said predetermined number of said processing units having a higher associated task priority after each of said previous processing unit has completed its service of said interrupt signal.
Claim 10
Dependent Claim
180 words
An interrupt controller for a symmetrical multiprocessing system comprising: at least one interrupt channel configured to receive an interrupt signal; a plurality of CPU channels configured to distribute selected interrupt signals to dedicated processing units; and a central controller coupled to said at least one interrupt and to said plurality of CPU channels, wherein said central controller is configured to determine a designated processing unit of a predetermined number of processing units having a lowest task priority level and to provide said interrupt to said designated processing unit, and is configured to provide subsequently said interrupt signal to a subsequent processing unit of a remaining number of said predetermined number of said processing units having a higher associated task priority after said designated processing unit completes its service of said interrupt signal and is further configured to provide said interrupt signal to each next subsequent processing unit of said remaining number of said predetermined number of said processing units having a higher associated task priority after each of said previous processing unit has completed its service of said interrupt signal.
Claim 11
Dependent Claim
26 words
The interrupt controller as recited in claim 8 wherein said subsequent processing unit has the lowest task priority level of a remaining group of processing units.
Claim 12
Dependent Claim
33 words
The interrupt controller as recited in claim 8 wherein said plurality of CPU channels each include a current task priority register for storing the current task priority level of an associated processing unit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-17 | 2000-09-16 | 2001-03-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-17 | 2004-09-16 | 2005-03-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-17 | 2008-09-16 | 2009-03-18 | $7700.00 | Window Closed / Lapsed |