Multiport high speed memory having contention arbitration capability without standby delay

Claim 2

A multiport high speed memory circuit including: a plurality of ports including a first port and a second port; an address means for providing a plurality of physical addresses to said plurality of ports; a memory array defining a plurality of memory lines for storing computer data, each memory line having a plurality of memory wordlines for accessing said memory line, said plurality of memory wordlines including a first wordline for said first port and a second wordline for said second port; a plurality of decoders including a decoder for each of said plurality of ports, each decoder coupled to one of said plurality of ports to receive one of the plurality of physical addresses, each of said decoders including a circuit for decoding said plurality of physical addresses to select one of a plurality of decoder output lines; a plurality of distributed bit comparators coupled to the outputs of the decoders, each distributed bit comparator being coupled to receive at least two of the decoder output lines associated with a single memory line, compare said decoder output lines, and supply a comparison signal to a plurality of line drivers responsive to said comparison; said plurality of line drivers including a first group of line drivers for the first port and a second group of line drivers for the second port, each line driver in said first group coupled to drive a preselected first wordline of a memory array for the first port and receiving an input line from the decoders for the first port, each line driver in said second group being coupled to drive a preselected second wordline for the second port and receiving an input line from the decoder for the second port and also receiving from the distributed bit comparators a comparison signal that, if asserted, prevents said line driver in the second group from driving its respective wordline.

Claim 3

A multiport high speed memory circuit including: a plurality of ports including a first port and a second port; an address means for providing a plurality of physical addresses to said plurality of ports; an address comparator circuit coupled to the physical address means for comparing each of said addresses to determine if there is a match between any two of said addresses, and in response thereto to provide a plurality of gate control signals; a memory array defining a plurality of memory lines for storing computer data, each memory line having a plurality of memory wordlines for accessing said memory line, said plurality of memory wordlines including a first wordline for said first port and a second wordline for said second port; a plurality of decoders including a decoder for each of said plurality of ports, each decoder coupled to one of said plurality of ports to receive one of the plurality of physical addresses, each of said decoders including a circuit for decoding said plurality of physical addresses to select one of a plurality of decoder output lines; a plurality of distributed bit comparators coupled to the outputs of the decoders, each distributed bit comparator being coupled to receive at least two of the decoder output lines associated with a single memory line, compare said decoder output lines, and supply a comparison signal to a plurality of line drivers responsive to said comparison; said plurality of line drivers including a first group of line drivers for the first port and the second group of line drivers for the second port, each line driver in said first group coupled to drive a preselected first wordline of a memory array for the first port and receiving an input line from the decoders for the first port, each line driver in said second group being coupled to drive a preselected second wordline for the second port and receiving an input line from the decoder for the second port and also receiving from the distributed bit comparators a comparison signal that, if asserted, prevents said line driver in the second group from driving its respective memory line; and a gate circuit coupled to receive each of a plurality of memory lines output from the memory array, said gate circuit also coupled to receive the gate control signals, and responsive thereto, to route the data in said plurality of memory lines to a correct output line corresponding to the port that addressed said data.

Claim 4

A multiport high speed memory circuit including: a plurality of ports including a first port and a second port; an address means for providing a plurality of physical addresses to said plurality of ports; an address comparator circuit coupled to the physical address means for comparing each of said addresses to determine if there is a match between any two of said addresses, and in response thereto to provide a plurality of gate control signals; a memory array defining a plurality of memory lines for storing computer data, each memory line having a plurality of memory wordlines for accessing said memory line, said plurality of memory wordlines including a first wordline for said first port and a second wordline for said second port; a plurality of decoders including a decoder for each of said plurality of ports, each decoder coupled to one of said plurality of ports to receive one of the plurality of physical addresses, each of said decoders including a circuit for decoding said plurality of physical addresses to select one of a plurality of decoder output lines; a plurality of distributed bit comparators coupled to the outputs of the decoders, each distributed bit comparator being coupled to receive at least two of the decoder output lines associated with a single memory line, compare said decoder output lines, and supply a comparison signal to a plurality of line drivers responsive to said comparison; said plurality of line drivers including a first group of line drivers for the first port and the second group of line drivers for the second port, each line driver in said first group coupled to drive a preselected first wordline of a memory array for the first port and receiving an input line from the decoders for the first port, each line driver in said second group being coupled to drive a preselected second wordline for the second port and receiving an input line from the decoder for the second port and also receiving from the distributed bit comparators a comparison signal that, if asserted, prevents said line driver in the second group from driving its respective memory line; and a gate circuit coupled to receive each of a plurality of memory lines output from the memory array, said gate circuit also coupled to receive the gate control signals, and responsive thereto, to route the data in said plurality of memory lines to a correct output line corresponding to the port that addressed said data.