Multiport semiconductor memory including an address comparator

Claim 1

A semiconductor memory device comprising: a memory cell array made up of a plurality of memory cells arrayed in a matrix fashion; two groups of select lines for selecting the memory cells arrayed in rows in the memory cell array; first and second groups of data line pairs each connected to a plurality of memory cells in said array of memory cells; first and second row decoders for respectively selecting and driving the select lines in said two select line groups in response to independent row address signals; an address coincidence detecting circuit for detecting a coincidence of the address signal respectively supplied to said first and second row decoders; a first control circuit for prohibiting a selected one of said first and second row decoders from performing the select line drive operations when said address coincidence circuit detects a coincidence between the independent row address signals; first and second data line select circuits supplied with independent column address signals; a second control circuit controlled by an output signal of said address coincidence detecting circuit for causing said first and second data line select circuits to independently select one data line pair of said first and second groups of data line pairs respectively when a coincidence between said row address signals is not detected and for causing said first and second data line select circuits to select the same data line pair from one of said first and second groups of data line pairs when a coincidence between said row address signals is detected; and first and second read/write circuits coupled with the data lines respectively selected by said first and second data line select circuits.