Biquadratic switched-capacitor filter using single operational amplifier

Claim 2

A biquadratic switched-capacitor filter having a non-inverting input terminal, an inverting input terminal, a non-inverting output terminal, and an inverting output, terminal, the biquadratic switched-capacitor filter comprising: an operational amplifier having a non-inverting input, an inverting input, a non-inverting output, and an inverting output; a first switched-capacitor circuit, controlled by a first clock signal and a second clock signal, coupled between the inverting input terminal of the biquadratic switched-capacitor filter and the inverting input of the operational amplifier; a second switched-capacitor circuit, controlled by the first clock signal and the second clock signal, coupled between the inverting input terminal of the biquadratic switched-capacitor filter and the inverting input of the operational amplifier; a third switched-capacitor circuit, controlled by the first clock signal and the second clock signal, coupled between the non-inverting input terminal of the biquadratic switched-capacitor filter and the non-inverting input of the operational amplifier; a fourth switched-capacitor circuit, controlled by the first clock signal and the second clock signal, coupled between the non-inverting input terminal of the biquadratic switched-capacitor filter and the non-inverting input of the operational amplifier; a fifth switched-capacitor circuit, controlled by the first clock signal and the second clock signal, coupled between the inverting input of the operational amplifier and the non-inverting output of the operational amplifier; a sixth switched capacitor circuit, controlled by the first clock signal and the second clock signal, coupled between the non-inverting input of the operational amplifier and the inverting output of the operational amplifier; a seventh switched-capacitor circuit, controlled by a third clock signal and a fourth clock signal, coupled between the inverting output of the operational amplifier and the inverting input of the operational amplifier; an eighth switched-capacitor circuit, controlled by a fifth clock signal and a sixth clock signal, coupled between the inverting output of the operational amplifier and the inverting input of the operational amplifier; a ninth switched-capacitor circuit, controlled by the third clock signal and the fourth clock signal, coupled between the non-inverting output of the operational amplifier and the non-inverting input of the operational amplifier; a tenth switched-capacitor circuit, controlled by the fifth clock signal and the sixth clock signal, coupled between the non-inverting output of the operational amplifier and the non-inverting input of the operational amplifier; a first feedback capacitor, coupled between the non-inverting output of the operational amplifier and the inverting input of the operational amplifier; a second feedback capacitor, coupled between the inverting output of the operational amplifier and the non-inverting input of the operational amplifier; a first switching device, controlled by the second clock signal, coupled between the non-inverting output of the operational amplifier and the non-inverting output terminal of the biquadratic switched-capacitor filter; and a second switching device, controlled by the second clock signal, coupled between the inverting output of the operational amplifier and the inverting output terminal of the biquadratic switched-capacitor filter; wherein the first clock signal and the second clock signal are two-phase, complementary but non-overlapping pulse trains with a reference period, the third clock signal is a pulse train with double the reference period and coincident with the first clock signal, the fourth clock signal is a pulse train that results from delaying the third clock signal by half the reference period, the fifth clock signal is a pulse train that results from delaying the fourth clock signal by half the reference period, and the sixth clock signal is a pulse train that results from delaying the fifth clock signal by half the reference period.

Claim 3

The biquadratic switched-capacitor filter of claim 1, wherein the first switched-capacitor circuit and the third switched-capacitor circuit are inverting switched-capacitor circuits, and the second switched-capacitor circuit and the fourth switched-capacitor circuit are non-inverting switched-capacitor circuits.

Claim 4

The biquadratic switched-capacitor filter of claim 1, wherein the first switched-capacitor circuit and the third switched-capacitor circuit are non-inverting switched-capacitor circuits, and the second switched-capacitor circuit and the fourth switched-capacitor circuit are inverting switched-capacitor circuits.

Claim 5

The biquadratic switched-capacitor filter of claim 1, wherein the fifth switched-capacitor circuit, the sixth switched-capacitor circuit, the seventh switched-capacitor circuit, the eighth switched-capacitor circuit, the ninth switched-capacitor circuit, and the tenth switched-capacitor circuit are inverting switched-capacitor circuits.

Claim 6

The biquadratic switched-capacitor filter of claim 4, wherein the first-switched-capacitor circuit and the third switched-capacitor circuit are inverting switched-capacitor circuits, and the second switched-capacitor circuit and the fourth switched-capacitor circuit are non-inverting switched-capacitor circuits.

Claim 7

The biquadratic switched-capacitor filter of claim 4, wherein the first switched-capacitor circuit and the third switched-capacitor circuit are non-inverting switched-capacitor circuits, and the second switched-capacitor circuit and the fourth switched-capacitor circuit are inverting switched-capacitor circuits.

Claim 8

The biquadratic switched-capacitor filter of claim 6, wherein the transfer function of the biquadratic switched-capacitor filter can be expressed as: ##EQU6## wherein CA is the capacitance of capacitors that reside in the first switched-capacitor circuit and in the third switched-capacitor circuit; CF is the capacitance of the first feedback capacitor and the second feedback capacitor; CB is the capacitance of capacitors that reside in the second switched-capacitor circuit and in the fourth switched-capacitor circuit; CR is the capacitance of capacitors that reside in the fifth switched-capacitor circuit and in the sixth switched-capacitor circuit; CX is the capacitance of capacitors that reside in the seventh switched-capacitor circuit, the eighth switched-capacitor circuit, the ninth switched-capacitor circuit, and the tenth switched-capacitor circuit.

Claim 9

The biquadratic switched-capacitor filter of claim 1, wherein the first switching device is a MOS transistor.

Claim 10

The biquadratic switched-capacitor filter of claim 1, wherein the second switching device is a MOS transistor.

Claim 11

The biquadratic switched-capacitor filter of claim 8, wherein the second switching device is a transistor.

Claim 12

A third-order sigma-delta modulator, comprising: means for receiving an input signal to the sigma-delta modulator; means for providing an output signal of the sigma-delta modulator; a D/A converter for transforming the output signal from digital form into a feedback signal of analog form; a first adder for adding the inverse of the feedback signal to the input signal, and generating a first signal indicative thereof; a biquadratic switched-capacitor filter having an input for receiving the first signal and providing a second signal as its output, the biquadratic switched-capacitor filter comprising: an operational amplifier having a non-inverting input, an inverting input, a non-inverting output, and an inverting output; a first switched-capacitor circuit, which is controlled by a first clock signal and a second clock signal and coupled between the inverting input terminal of the biquadratic switched-capacitor filter and the inverting input of the operational amplifier; a second switched-capacitor circuit, which is controlled by the first clock signal and the second clock signal and coupled between the inverting input terminal of the biquadratic switched-capacitor filter and the inverting input of the operational amplifier; a third switched-capacitor circuit, which is controlled by the first clock signal and the second clock signal and coupled between the non-inverting input terminal of the biquadratic switched-capacitor filter and the non-inverting input of the operational amplifier; a fourth switched-capacitor circuit, which is controlled by the first clock signal and the second clock signal and coupled between the non-inverting input terminal of the biquadratic switched-capacitor filter and the non-inverting input of the operational amplifier; a fifth switched-capacitor circuit, which is controlled by the first clock signal and the second clock signal and coupled between the inverting input of the operational amplifier and the non-inverting output of the operational amplifier; a sixth switched-capacitor circuit, which is controlled by the first clock signal and the second clock signal and coupled between the non-inverting input of the operational amplifier and the inverting output of the operational amplifier; a seventh switched-capacitor circuit, which is controlled by a third clock signal and a fourth clock signal and coupled between the inverting output of the operational amplifier and the inverting input of the operational amplifier; an eighth switched-capacitor circuit, which is controlled by a fifth clock signal and a sixth clock signal and coupled between the inverting output of the operational amplifier and the inverting input of the operational amplifier; a ninth switched-capacitor circuit, which is controlled by the third clock signal and the fourth clock signal and coupled between the non-inverting output of the operational amplifier and the non-inverting input of the operational amplifier; a tenth switched-capacitor circuit, which is controlled by the fifth clock signal and the sixth clock signal and coupled between the non-inverting output of the operational amplifier and the non-inverting input of the operational amplifier; a first feedback capacitor, which is coupled between the non-inverting output of the operational amplifier and the inverting input of the operational amplifier; a second feedback capacitor, which is coupled between the inverting output of the operational amplifier and the non-inverting input of the operational amplifier; a first switching device, which is controlled by the second clock signal and coupled between the non-inverting output of the operational amplifier and the non-inverting output terminal of the biquadratic switched-capacitor filter; and a second switching device, which is controlled by the second clock signal and coupled between the inverting output of the operational amplifier and the inverting output terminal of the biquadratic switched-capacitor filter; wherein the first clock signal and the second clock signal are two-phase, complementary but non-overlapping pulse trains with a reference period, the third clock signal is a pulse train with double the reference period and coincident with the first clock signal, the fourth clock signal is a pulse train that results from delaying the third clock signal by half the reference period, the fifth clock signal is a pulse train that results from delaying the fourth clock signal by half the reference period, and the sixth clock signal is a pulse train that results from delaying the fifth clock signal by half the reference period; a second adder for adding the inverse of the feedback signal to the second output from the biquadratic switched-capacitor circuit, and generating a third signal indicative thereof; a multiplier for multiplying the third signal by a number and generating a fourth signal indicative thereof; a first order filter for filtering the fourth reference signal and generating a fifth signal indicative thereof; and a quantizer for quantizing the fifth signal and generating the output signal of the third-order sigma-delta modulator.

Claim 13

A third-order sigma-delta modulator, comprising: means for receiving an input signal to the sigma-delta modulator; means for providing an output signal of the sigma-delta modulator; a D/A converter for transforming the output signal from digital form into a feedback signal of analog form; a first adder for adding the inverse of the feedback signal to the input signal, and generating a first signal indicative thereof; a biquadratic switched-capacitor filter having an input for receiving the first signal and providing a second signal as its output, the biquadratic switched-capacitor filter comprising: an operational amplifier having a non-inverting input, an inverting input, a non-inverting output, and an inverting output; a first switched-capacitor circuit, which is controlled by a first clock signal and a second clock signal and coupled between the inverting input terminal of the biquadratic switched-capacitor filter and the inverting input of the operational amplifier; a second switched-capacitor circuit, which is controlled by the first clock signal and the second clock signal and coupled between the inverting input terminal of the biquadratic switched-capacitor filter and the inverting input of the operational amplifier; a third switched-capacitor circuit, which is controlled by the first clock signal and the second clock signal and coupled between the non-inverting input terminal of the biquadratic switched-capacitor filter and the non-inverting input of the operational amplifier; a fourth switched-capacitor circuit, which is controlled by the first clock signal and the second clock signal and coupled between the non-inverting input terminal of the biquadratic switched-capacitor filter and the non-inverting input of the operational amplifier; a fifth switched-capacitor circuit, which is controlled by the first clock signal and the second clock signal and coupled between the inverting input of the operational amplifier and the non-inverting output of the operational amplifier; a sixth switched-capacitor circuit, which is controlled by the first clock signal and the second clock signal and coupled between the non-inverting input of the operational amplifier and the inverting output of the operational amplifier; a seventh switched-capacitor circuit, which is controlled by a third clock signal and a fourth clock signal and coupled between the inverting output of the operational amplifier and the inverting input of the operational amplifier; an eighth switched-capacitor circuit, which is controlled by a fifth clock signal and a sixth clock signal and coupled between the inverting output of the operational amplifier and the inverting input of the operational amplifier; a ninth switched-capacitor circuit, which is controlled by the third clock signal and the fourth clock signal and coupled between the non-inverting output of the operational amplifier and the non-inverting input of the operational amplifier; a tenth switched-capacitor circuit, which is controlled by the fifth clock signal and the sixth clock signal and coupled between the non-inverting output of the operational amplifier and the non-inverting input of the operational amplifier; a first feedback capacitor, which is coupled between the non-inverting output of the operational amplifier and the inverting input of the operational amplifier; a second feedback capacitor, which is coupled between the inverting output of the operational amplifier and the non-inverting input of the operational amplifier; a first switching device, which is controlled by the second clock signal and coupled between the non-inverting output of the operational amplifier and the non-inverting output terminal of the biquadratic switched-capacitor filter; and a second switching device, which is controlled by the second clock signal and coupled between the inverting output of the operational amplifier and the inverting output terminal of the biquadratic switched-capacitor filter; wherein the first clock signal and the second clock signal are two-phase, complementary but non-overlapping pulse trains with a reference period, the third clock signal is a pulse train with double the reference period and coincident with the first clock signal, the fourth clock signal is a pulse train that results from delaying the third clock signal by half the reference period, the fifth clock signal is a pulse train that results from delaying the fourth clock signal by half the reference period, and the sixth clock signal is a pulse train that results from delaying the fifth clock signal by half the reference period; a second adder for adding the inverse of the feedback signal to the second output from the biquadratic switched-capacitor circuit, and generating a third signal indicative thereof; a multiplier for multiplying the third signal by a number and generating a fourth signal indicative thereof; a first order filter for filtering the fourth reference signal and generating a fifth signal indicative thereof; and a quantizer for quantizing the fifth signal and generating the output signal of the third-order sigma-delta modulator.

Claim 14

The sigma-delta modulator of claim 11 wherein in the switched-capacitor filter the first switched-capacitor circuit and the third switched-capacitor circuit are-inverting switched-capacitor circuits, and the second switched-capacitor circuit and the fourth switched-capacitor circuit are non-inverting switched-capacitor circuits.

Claim 15

The sigma-delta modulator of claim 11 wherein in the switched-capacitor filter the first switched-capacitor circuit and the third switched-capacitor circuit are non-inverting switched-capacitor circuits, and the second switched-capacitor circuit and the fourth switched-capacitor circuit are inverting switched-capacitor circuits.

Claim 16

The sigma-delta modulator of claim 11 wherein in the switched-capacitor filter the fifth switched-capacitor circuit, the sixth switched-capacitor circuit, the seventh switched-capacitor circuit, the eighth switched-capacitor circuit, the ninth switched-capacitor circuit, and the tenth switched-capacitor circuit are inverting switched-capacitor circuits.

Claim 17

The sigma-delta modulator of claim 14 wherein in the switched-capacitor filter the first switched-capacitor circuit and the third switched-capacitor are inverting switched-capacitor circuits, and the second switched-capacitor circuit and the fourth switched-capacitor circuit are non-inverting switched-capacitor circuits.

Claim 18

The sigma-delta modulator of claim 14 wherein in the switched-capacitor filter the first switched-capacitor circuit and the third switched-capacitor circuit are non-inverting switched-capacitor circuits, and the second switched-capacitor circuit and the fourth switched-capacitor circuit are inverting switched-capacitor circuits.

Claim 19

The sigma-delta modulator of claim 16 wherein in the switched-capacitor filter the transfer function of the biquadratic switched-capacitor filter can be expressed as: ##EQU7## wherein CA is the capacitance of capacitors that reside in the first switched-capacitor circuit and in the third switched-capacitor circuit; CF is the capacitance of the first feedback capacitor and the second feedback capacitor; CB is the capacitance of capacitors that reside in the second switched-capacitor circuit and in the fourth switched-capacitor circuit; CR is the capacitance of capacitors that reside in the fifth switched-capacitor circuit and in the sixth switched-capacitor circuit; CX is the capacitance of capacitors that reside in the seventh switched-capacitor circuit, the eighth switched-capacitor circuit, the ninth switched-capacitor circuitry and, the tenth switched-capacitor circuit.

Claim 20

The sigma-delta modulator of claim 11 wherein in the switched-capacitor filter the first switching device is a MOS transistor.

Claim 21

The sigma-delta modulator of claim 11 wherein in the switched-capacitor filter the second switching device is a MOS transistor.

Claim 22

The sigma-delta modulator of claim 18 wherein in the switched-capacitor filter the second switching device is a MOS transistor.