Output driver with level shifting and voltage protection

Claim 2

An output driver circuit comprising: first and second complementary data terminals; an pull-terminal; a pull-up transistor and a pull-down transistor which are coupled to the output terminal and have first and second control terminals, respectively, with the second control terminal coupled to the second data terminal; a differential transistor pair defining first and second current paths and having control terminals coupled to the first and second data terminals, respectively; a cross coupled transistor pair coupled in the first and second current paths and having a control output terminal coupled to the control terminal of the pull-up transistor; and a first voltage protection transistor coupled between the pull-up transistor and the output terminal and having a control terminal coupled to the second current path, between the differential transistor pair and the cross coupled transistor pair.

Claim 3

The output driver circuit of claim 1 wherein: the cross coupled transistor pair comprises first and second p-channel transistors which are coupled in the first and second current paths, respectively; and the differential transistor pair comprises third and fourth p-channel transistors which are coupled in the first and second current paths, respectively.

Claim 4

The output driver circuit of claim 2 and further comprising: a first voltage reference terminal having a selected voltage level, and second and third n-channel voltage protection transistors coupled in the first and second current paths, respectively, between the differential transistor pair and the cross coupled transistor pair and having control terminals coupled to the first reference voltage terminal.

Claim 5

The output driver circuit of claim 1 and further comprising: a first voltage reference terminal having a selected voltage level; a first charge boosting transistor coupled between the first voltage reference terminal and the first current path at a node between the cross coupled transistor pair and the differential transistor pair, wherein the first charge boosting transistors is biased by the second complementary data terminal; and a second charge boosting transistor coupled between the first voltage reference terminal and the second current path at a node between the cross coupled transistor pair and the differential transistor pair, wherein the second charge boosting transistors is biased by the first complementary data terminal.

Claim 6

The output driver circuit of claim 1 wherein the output driver stage further comprises: a first voltage reference terminal having a selected voltage level; and a second voltage protection transistor coupled between the output terminal and the pull-down transistor and having a gate terminal coupled to the first voltage reference terminal.

Claim 7

The output driver of claim 1 and further comprising: a first voltage reference terminal; and an n-channel transistor coupled between the control terminal of the first voltage protection transistor and the second current path and having a control terminal coupled to the first voltage reference terminal.

Claim 8

An output driver circuit comprising: first and second voltage supply terminals; first and second complementary data terminals; an output terminal; a pull-up transistor coupled between the first voltage supply terminal and the output terminal and having a first control terminal; a pull-down transistor coupled between the second voltage supply terminal and the output terminal and having a second control terminal coupled to the second data terminal; first and second predriver current paths; a pull-down, p-channel differential transistor pair coupled between the second voltage supply terminal and the first and second current paths and having control terminals coupled to the first and second data terminals, respectively; and a p-channel cross coupled transistor pair coupled in the first and second current paths between the first voltage supply terminal and the differential transistor pair and having a control output terminal coupled to the control terminal of the pull-up transistor.

Claim 9

An output driver circuit comprising: first and second voltage supply terminals; first and second complementary data terminals; an output terminal; a pull-up transistor coupled between the first voltage supply terminal and the output terminal and having a first control terminal; a pull-down transistor coupled between the second voltage supply terminal and the output terminal and having a second control terminal coupled to the second data terminal; first and second predriver current paths; a pull-down, p-channel differential transistor pair coupled between the second voltage supply terminal and the first and second current paths and having control terminals coupled to the first and second data terminals, respectively; and a p-channel cross coupled transistor pair coupled in the first and second current paths between the first voltage supply terminal and the differential transistor pair and having a control output terminal coupled to the control terminal of the pull-up transistor.

Claim 10

The output driver circuit of claim 7 and further comprising: a first voltage reference terminal having a selected voltage level; and first and second n-channel voltage protection transistors coupled in the first and second current paths, respectively, between the differential transistor pair and the cross coupled transistor pair and having control terminals coupled to the first reference voltage terminal.

Claim 11

The output driver circuit of claim 7 and further comprising: a first voltage protection transistor coupled between the pull-up transistor and the output terminal and having a control terminal coupled to the second current path, between the differential transistor pair and the cross coupled transistor pair.

Claim 12

The output driver of claim 9 and further comprising: a first voltage reference terminal; and an n-channel transistor coupled between the control terminal of the first voltage protection transistor and the second current path and having a control terminal coupled to the first voltage reference terminal.

Claim 13

An output driver circuit comprising: first and second complementary data terminals; first, second and third reference voltage terminals; an output terminal; a pull-up transistor and a pull-down transistor which are coupled to the output terminal and have first and second control terminals, respectively, with the second control terminal coupled to the second data terminal; first and second differential transistors defining first and second current paths and having control terminals coupled to the first and second data terminals, respectively; first and second cross coupled transistors coupled in the first and second current paths, respectively, and having a control output terminal which is coupled to the control terminal of the pull-up transistor; first and second voltage protection transistors coupled in the first and second current paths between the first and second differential transistors and the first and second cross coupled transistors, respectively, and having control terminals coupled to the first voltage reference terminal, and a bias circuit comprising: at least one diode-connected transistor coupled between the second voltage reference terminal and the first voltage reference terminal; a discharge transistor coupled between the first voltage reference terminal and the third voltage reference terminal and having a control terminal; and a buffer circuit coupled between the first voltage reference terminal and the control terminal of the discharge transistor.

Claim 14

An output driver circuit comprising: first and second complementary data terminals; first, second and third reference voltage terminals; an output terminal; a pull-up transistor and a pull-down transistor which are coupled to the output terminal and have first and second control terminals, respectively, with the second control terminal coupled to the second data terminal; first and second differential transistors defining first and second current paths and having control terminals coupled to the first and second data terminals, respectively; first and second cross coupled transistors coupled in the first and second current paths, respectively, and having a control output terminal which is coupled to the control terminal of the pull-up transistor; first and second voltage protection transistors coupled in the first and second current paths between the first and second differential transistors and the first and second cross coupled transistors, respectively, and having control terminals coupled to the first voltage reference terminal, and a bias circuit comprising: at least one diode-connected transistor coupled between the second voltage reference terminal and the first voltage reference terminal; a discharge transistor coupled between the first voltage reference terminal and the third voltage reference terminal and having a control terminal; and a buffer circuit coupled between the first voltage reference terminal and the control terminal of the discharge transistor.

Claim 15

The output driver circuit of claim 11 the buffer circuit comprises first and second inverters coupled together in series between the first voltage reference terminal and the control terminal of the discharge transistor.

Claim 16

The output driver circuit of claim 12 wherein: the first inverter comprises a p-channel transistor coupled in series with three n-channel transistors between the second voltage reference terminal and the third voltage reference terminal; and the second inverter comprises three p-channel transistors coupled in series with an n-channel transistor between the second voltage reference terminal and the third voltage reference terminal.