Central processing unit with integrated graphics functions

Claim 1

An apparatus, comprising: a register file including a first and a second register for storing a first and a second plurality of graphics data, and a third register for storing a pixel distance value; and pixel distance computation circuitry coupled to the register file, including a plurality of subtractor assemblies coupled in parallel to an hierarchy of carry save adders, for executing a pixel distance computation instruction, said pixel distance computation instruction simultaneously computing absolute differences of the first and second plurality of graphic data using the subtractor assemblies, and accumulating their absolute differences into the third register to form the pixel distance value using the carry save adders.

Claim 2

An apparatus, comprising: a register file including a first and a second register for storing a first and a second plurality of graphics data, and a third register for storing a pixel distance value; and pixel distance computation circuitry coupled to the register file, including a plurality of subtractor assemblies coupled in parallel to an hierarchy of carry save adders, for executing a pixel distance computation instruction, said pixel distance computation instruction simultaneously computing absolute differences of the first and second plurality of graphic data using the subtractor assemblies, and accumulating their absolute differences into the third register to form the pixel distance value using the carry save adders.

Claim 5

An apparatus, comprising: a register file including a first and a second register for storing a first and a second plurality of graphics data addresses respectively, and a third register for storing a plurality of edge masks; and an integer execution unit (IEU) coupled to the register file for executing a graphics data edge handling instruction the graphics data edge handling instruction simultaneously generating and storing the edge masks in the third register, using the contents of the first and second registers, each mask being generated by conditionally performing a logical AND operation against a first and a second intermediate edge mask, depending on how a first and a second plurality of corresponding higher order bits of the first and second registers compare to each other, the first and second intermediate edge masks being generated in accordance to a first and a second plurality of corresponding lower order bits of the first and second registers.

Claim 6

An apparatus, comprising: a register file including a first and a second register for storing a first and a second plurality of graphics data addresses respectively, and a third register for storing a plurality of edge masks; and an integer execution unit (IEU) coupled to the register file for executing a graphics data edge handling instruction the graphics data edge handling instruction simultaneously generating and storing the edge masks in the third register, using the contents of the first and second registers, each mask being generated by conditionally performing a logical AND operation against a first and a second intermediate edge mask, depending on how a first and a second plurality of corresponding higher order bits of the first and second registers compare to each other, the first and second intermediate edge masks being generated in accordance to a first and a second plurality of corresponding lower order bits of the first and second registers.

Claim 9

An apparatus, comprising: a register file including a first register for storing an encoded value, a second register for storing a plurality of 3-D fixed point addresses, and a third register for storing a blocked byte address; and an integer execution unit (IEU) coupled to the register file for executing a graphics data three-dimensional (3-D) array addressing instruction the graphics data 3-D array addressing instruction generating and storing the blocked byte address in the third register using the encoded value and the 3-D fixed point addresses in the first and second registers, the blocked byte address being generated by concatenating a first and a second intermediate value, which are generated from various predetermined portions of the 3-D fixed point addresses.

Claim 10

An apparatus, comprising: a register file including a first register for storing an encoded value, a second register for storing a plurality of 3-D fixed point addresses, and a third register for storing a blocked byte address; and an integer execution unit (IEU) coupled to the register file for executing a graphics data three-dimensional (3-D) array addressing instruction the graphics data 3-D array addressing instruction generating and storing the blocked byte address in the third register using the encoded value and the 3-D fixed point addresses in the first and second registers, the blocked byte address being generated by concatenating a first and a second intermediate value, which are generated from various predetermined portions of the 3-D fixed point addresses.

Claim 11

An apparatus, comprising: a floating pointer register file (FPRF) for storing floating point and graphics data; a integer register file (IRF) for storing integer and graphics data addresses; a floating point execution unit (FPU) coupled to said FPRF for executing a plurality of non-graphics floating point instructions; an integer execution unit (IEU) coupled to said IRF for executing a plurality of non-graphics integer instructions, a plurality of graphics data edge handling instructions, and a plurality of graphics data three-dimensional (3-D) array addressing instructions, each of said graphics data edge handling instructions simultaneously generating multiple edge masks for multiple pairs of graphics data addresses, and each of said graphics data 3-D array addressing instructions converts multiple 3-D graphics data array fixed point addresses to a blocked byte address; and a graphics execution unit (GRU) coupled to said FPRF for executing a plurality of graphics data conversion instructions, a plurality of graphics data misaligned address calculation instructions, a plurality of graphics data alignment instructions, and a pixel distance computation instruction, each of said graphics data conversion instructions simultaneously packing multiple graphics data from a first partitioned graphics data format to a second partitioned graphics data format, scaling shifting and clipping operations in accordance to a scaling factor, each of said graphics data misaligned address calculation instructions calculating an address of a block of misaligned graphics data and an address alignment offset, each of said graphics data alignment instructions aligning a block of misaligned graphics data in accordance to an address aligmnent offset, and said pixel distance computation instruction simultaneously computing absolute differences of multiple pairs of graphic data and accumulating their absolute differences.

Claim 12

An apparatus, comprising: a floating pointer register file (FPRF) for storing floating point and graphics data; a integer register file (IRF) for storing integer and graphics data addresses; a floating point execution unit (FPU) coupled to said FPRF for executing a plurality of non-graphics floating point instructions; an integer execution unit (IEU) coupled to said IRF for executing a plurality of non-graphics integer instructions, a plurality of graphics data edge handling instructions, and a plurality of graphics data three-dimensional (3-D) array addressing instructions, each of said graphics data edge handling instructions simultaneously generating multiple edge masks for multiple pairs of graphics data addresses, and each of said graphics data 3-D array addressing instructions converts multiple 3-D graphics data array fixed point addresses to a blocked byte address; and a graphics execution unit (GRU) coupled to said FPRF for executing a plurality of graphics data conversion instructions, a plurality of graphics data misaligned address calculation instructions, a plurality of graphics data alignment instructions, and a pixel distance computation instruction, each of said graphics data conversion instructions simultaneously packing multiple graphics data from a first partitioned graphics data format to a second partitioned graphics data format, scaling shifting and clipping operations in accordance to a scaling factor, each of said graphics data misaligned address calculation instructions calculating an address of a block of misaligned graphics data and an address alignment offset, each of said graphics data alignment instructions aligning a block of misaligned graphics data in accordance to an address aligmnent offset, and said pixel distance computation instruction simultaneously computing absolute differences of multiple pairs of graphic data and accumulating their absolute differences.

Claim 13

A method of executing graphics instructions by a central processing unit (CPU), comprising the step of: executing a graphics data edge handling instruction by simultaneously generate multiple edge masks for multiple pairs of graphics data addresses, using a register file and an integer execution unit (IEU) coupled to each other, and disposed on said CPU, the register file including a first and a second register for storing the graphics data addresses, and a third register for storing the edge masks, each mask being generated by conditionally performing a logical AND operation against a first and a second intermediate edge mask, depending on how a first and a second plurality of corresponding higher order bits of the first and second registers compare to each other, the first and second intermediate edge masks being generated in accordance to a first and a second plurality of corresponding lower order bits of the first and second registers.

Claim 14

A method of executing graphics instructions by a central processing unit (CPU), comprising the step of: executing a graphics data edge handling instruction by simultaneously generate multiple edge masks for multiple pairs of graphics data addresses, using a register file and an integer execution unit (IEU) coupled to each other, and disposed on said CPU, the register file including a first and a second register for storing the graphics data addresses, and a third register for storing the edge masks, each mask being generated by conditionally performing a logical AND operation against a first and a second intermediate edge mask, depending on how a first and a second plurality of corresponding higher order bits of the first and second registers compare to each other, the first and second intermediate edge masks being generated in accordance to a first and a second plurality of corresponding lower order bits of the first and second registers.

Claim 16

A method of executing graphics instructions by a central processing unit (CPU), comprising the step of executing a graphics data three-dimensional (3-D) array addressing instruction to convert multiple 3-D graphics data array fixed point addresses to a blocked byte address using a register file and an integer execution unit (IEU) coupled to each other and disposed on said CPU, the register file including a first register for storing an encoded value, a second register for storing the fixed point addresses, and a third register for storing the blocked byte address, the blocked byte address being generated by concatenating a first and a second intermediate value, which are generated from various predetermined portions of the fixed point addresses.

Claim 17

A method of executing graphics instructions by a central processing unit (CPU), comprising the step of executing a graphics data three-dimensional (3-D) array addressing instruction to convert multiple 3-D graphics data array fixed point addresses to a blocked byte address using a register file and an integer execution unit (IEU) coupled to each other and disposed on said CPU, the register file including a first register for storing an encoded value, a second register for storing the fixed point addresses, and a third register for storing the blocked byte address, the blocked byte address being generated by concatenating a first and a second intermediate value, which are generated from various predetermined portions of the fixed point addresses.

Claim 18

A method of executing graphics instructions by a central processing unit (CPU), comprising the steps of: storing a scaling factor for graphics data in a graphics status register (GSR) disposed in said CPU; executing a plurality of graphics data packing instructions to pack multiple graphics data from a first partitioned graphics data format to a second partitioned graphics data format, scaling shifting and clipping operations in accordance to said stored scaling factor using dedicated graphics data conversion circuitry disposed in said CPU; executing a plurality of graphics data misaligned address calculation instructions to calculate an address of a block of misaligned graphics data and an address alignment offset using dedicated graphics data alignment circuitry disposed in said CPU, said address alignment offset being stored into said GSR; executing a plurality of graphics data alignment instructions to align a block of misaligned graphics data in accordance to said stored address alignment offset using said dedicated graphics data alignment circuitry; executing a pixel distance computation instruction to simultaneously compute absolute differences of multiple pairs of graphics data and accumulate their absolute differences using dedicated pixel distance computation circuitry disposed in said CPU; executing a plurality of graphics data edge handling instructions to simultaneously generate multiple edge masks for multiple pairs of graphics data addresses using an integer execution unit (IEU) disposed on said CPU; and executing a plurality of graphics data three-dimensional (3-D) array addressing instructions to convert multiple 3-D graphics data array fixed point addresses to a blocked byte address using said IEU.

Claim 19

A method of executing graphics instructions by a central processing unit (CPU), comprising the steps of: storing a scaling factor for graphics data in a graphics status register (GSR) disposed in said CPU; executing a plurality of graphics data packing instructions to pack multiple graphics data from a first partitioned graphics data format to a second partitioned graphics data format, scaling shifting and clipping operations in accordance to said stored scaling factor using dedicated graphics data conversion circuitry disposed in said CPU; executing a plurality of graphics data misaligned address calculation instructions to calculate an address of a block of misaligned graphics data and an address alignment offset using dedicated graphics data alignment circuitry disposed in said CPU, said address alignment offset being stored into said GSR; executing a plurality of graphics data alignment instructions to align a block of misaligned graphics data in accordance to said stored address alignment offset using said dedicated graphics data alignment circuitry; executing a pixel distance computation instruction to simultaneously compute absolute differences of multiple pairs of graphics data and accumulate their absolute differences using dedicated pixel distance computation circuitry disposed in said CPU; executing a plurality of graphics data edge handling instructions to simultaneously generate multiple edge masks for multiple pairs of graphics data addresses using an integer execution unit (IEU) disposed on said CPU; and executing a plurality of graphics data three-dimensional (3-D) array addressing instructions to convert multiple 3-D graphics data array fixed point addresses to a blocked byte address using said IEU.

Claim 20

A method of providing native graphics capabilities to a central processing unit (CPU), comprising the steps of: providing a graphics status register (GSR) in said CPU for storing a scaling factor for graphics data; providing dedicated graphics data conversion circuitry in said CPU for executing a plurality of graphics data packing instructions to pack multiple graphics data from a first partitioned graphics data format to a second partitioned graphics data format, scaling shifting and clipping operations in accordance to said stored scaling factor; providing dedicated graphics data alignment circuitry in said CPU for executing a plurality of graphics data misaligned address calculation instructions to calculate an address of a block of misaligned graphics data and an address alignment offset, said address alignment offset being stored into said GSR; providing circuitry to said dedicated graphics data alignment circuitry for executing a plurality of graphics data alignment instructions to align a block of misaligned graphics data in accordance to said stored address alignment offset; providing dedicated pixel distance computation circuitry disposed in said CPU for executing a pixel distance computation instruction to simultaneously compute absolute differences of multiple pairs of graphics data and accumulate their absolute differences; providing circuitry to an integer execution unit (IEU) in said CPU for executing a plurality of graphics data edge handling instructions to simultaneously generate multiple edge masks for multiple pairs of graphics data addresses; and providing circuitry to said IEU for executing a plurality of graphics data three-dimensional (3-D) array addressing instructions to convert multiple 3-D graphics data array fixed point addresses to a blocked byte address.

Claim 21

A method of providing native graphics capabilities to a central processing unit (CPU), comprising the steps of: providing a graphics status register (GSR) in said CPU for storing a scaling factor for graphics data; providing dedicated graphics data conversion circuitry in said CPU for executing a plurality of graphics data packing instructions to pack multiple graphics data from a first partitioned graphics data format to a second partitioned graphics data format, scaling shifting and clipping operations in accordance to said stored scaling factor; providing dedicated graphics data alignment circuitry in said CPU for executing a plurality of graphics data misaligned address calculation instructions to calculate an address of a block of misaligned graphics data and an address alignment offset, said address alignment offset being stored into said GSR; providing circuitry to said dedicated graphics data alignment circuitry for executing a plurality of graphics data alignment instructions to align a block of misaligned graphics data in accordance to said stored address alignment offset; providing dedicated pixel distance computation circuitry disposed in said CPU for executing a pixel distance computation instruction to simultaneously compute absolute differences of multiple pairs of graphics data and accumulate their absolute differences; providing circuitry to an integer execution unit (IEU) in said CPU for executing a plurality of graphics data edge handling instructions to simultaneously generate multiple edge masks for multiple pairs of graphics data addresses; and providing circuitry to said IEU for executing a plurality of graphics data three-dimensional (3-D) array addressing instructions to convert multiple 3-D graphics data array fixed point addresses to a blocked byte address.