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US5734613A
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Multi-port random access memory
Assignee: Nortel Networks Ltd
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Filing: 1996-09-19
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Granted: 1998-03-31
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Expires: 2016-09-19
Abstract
Abstract Disclosed is an architecture of a RAM (random access memory) with BIST (built-in self test) or functional test function. The RAM has a memory cell for storing differential or single-ended binary data and bit line signals are fully differential or single-ended. Shadow write is applied to read only and read-write bit lines. With the test function, port-to-port bit line shorts and port-to-port word line shorts are sensitized.
Inventors
- 👤 Garnet Frederick Randall Gibson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 18:24
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/02; G11C29/025; G11C29/04; G11C29/50; G11C8/00; G11C8/16; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
162 words
A multi-port RAM comprising RAM cells of m rows by n columns, each RAM cell including storage means for storing single-ended binary data, the RAM cells of each column being commonly coupled to a respective set of M data paths, m, n and M being integers, the multi-port RAM further comprising: access means for conducting data access to the RAM cells via the data paths; path select means for determining data paths so that data accessing via selected data paths is enabled and data accessing via non-selected data paths is disabled, the path select means comprising N groups of M switching means coupled to the respective M data paths, N being an integer; means for selectively applying a control signal to one or more groups of M switching means; and activating means for activating the M switching means of the group in response to the applied control signal, each activated switching means setting the respective data path to a predetermined voltage level.
Claim 2
Dependent Claim
162 words
A multi-port RAM comprising RAM cells of m rows by n columns, each RAM cell including storage means for storing single-ended binary data, the RAM cells of each column being commonly coupled to a respective set of M data paths, m, n and M being integers, the multi-port RAM further comprising: access means for conducting data access to the RAM cells via the data paths; path select means for determining data paths so that data accessing via selected data paths is enabled and data accessing via non-selected data paths is disabled, the path select means comprising N groups of M switching means coupled to the respective M data paths, N being an integer; means for selectively applying a control signal to one or more groups of M switching means; and activating means for activating the M switching means of the group in response to the applied control signal, each activated switching means setting the respective data path to a predetermined voltage level.
Claim 3
Dependent Claim
49 words
The multi-port RAM of claim 1, wherein: each of the switching means comprises a FET (field effect transistor), the drain-source of which is coupled between the respective data path and a terminal of the predetermined voltage level, the control signal being selectively applied to the gates of the FETs.
Claim 4
Dependent Claim
49 words
The multi-port RAM of claim 1, wherein the path select means comprises two groups of M switching means coupled to the respective M data paths, the means for selectively applying a control signal comprises means for alternately apply the control signal to the two groups of M switching means.
Claim 5
Dependent Claim
20 words
The multi-port RAM of claim 1, further comprising means for providing the ground potential level as the predetermined voltage level.
Claim 6
Dependent Claim
16 words
The multi-port RAM of claim 1, wherein the RAM cells are dynamic random access memory cells.
Claim 7
Dependent Claim
16 words
The multi-port RAM of claim 1, wherein the RAM cells are static random access memory cells.
Claim 8
Dependent Claim
113 words
A multi-port RAM comprising RAM cells of m rows by n columns, each RAM cell including storage means for storing single-ended binary data, the RAM cells of each column being commonly coupled to a respective set of M data paths, m, n and M being integers, the multi-port RAM further comprising: access means for reading single-ended binary data stored in the storage means via the data paths; path select means for determining data paths so that data reading via selected data paths is enabled and data reading via non-selected data paths is disabled; and test means for determining whether or not the single-ended binary data read from the storage means is expected data.
Claim 9
Dependent Claim
113 words
A multi-port RAM comprising RAM cells of m rows by n columns, each RAM cell including storage means for storing single-ended binary data, the RAM cells of each column being commonly coupled to a respective set of M data paths, m, n and M being integers, the multi-port RAM further comprising: access means for reading single-ended binary data stored in the storage means via the data paths; path select means for determining data paths so that data reading via selected data paths is enabled and data reading via non-selected data paths is disabled; and test means for determining whether or not the single-ended binary data read from the storage means is expected data.
Claim 10
Dependent Claim
140 words
A multi-port RAM comprising RAM cells of m rows by n columns, each RAM cell including storage means for storing single-ended binary data, the RAM cells of each column being commonly coupled to a respective set of M data paths, m, n and M being integers, the multi-port RAM further comprising: access means for storing single-ended binary data in the storage means via the data paths in a write mode and for reading the single-ended binary data stored in the storage means via the selected data paths in a read mode; path select means for determining data paths so that data storing or reading via selected data paths is enabled and data storing or reading via non-selected data paths is disabled; test means for determining whether or not the single-ended binary data read from the storage means is expected data.
Claim 11
Dependent Claim
140 words
A multi-port RAM comprising RAM cells of m rows by n columns, each RAM cell including storage means for storing single-ended binary data, the RAM cells of each column being commonly coupled to a respective set of M data paths, m, n and M being integers, the multi-port RAM further comprising: access means for storing single-ended binary data in the storage means via the data paths in a write mode and for reading the single-ended binary data stored in the storage means via the selected data paths in a read mode; path select means for determining data paths so that data storing or reading via selected data paths is enabled and data storing or reading via non-selected data paths is disabled; test means for determining whether or not the single-ended binary data read from the storage means is expected data.
Claim 12
Dependent Claim
105 words
A multi-port RAM comprising RAM cells of m rows by n columns, each RAM cell including storage means for storing single-ended binary data, the RAM cells of each column being commonly coupled to a respective set of M data paths, m, n and M being integers, the multi-port RAM further comprising: access means for conducting data access to the RAM cells via the data paths; path select means for determining data paths so that data accessing via the selected data paths is enabled and data accessing via the non-selected data paths is disabled; and test function means for testing data read from the storage means.
Claim 13
Dependent Claim
105 words
A multi-port RAM comprising RAM cells of m rows by n columns, each RAM cell including storage means for storing single-ended binary data, the RAM cells of each column being commonly coupled to a respective set of M data paths, m, n and M being integers, the multi-port RAM further comprising: access means for conducting data access to the RAM cells via the data paths; path select means for determining data paths so that data accessing via the selected data paths is enabled and data accessing via the non-selected data paths is disabled; and test function means for testing data read from the storage means.
Claim 14
Dependent Claim
26 words
The multi-port RAM of claim 9, wherein the test function means comprises OR function circuits, each receiving data from the respective port of each RAM cell.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-30 | 2001-09-29 | 2002-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-30 | 2005-09-29 | 2006-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-30 | 2009-09-29 | 2010-03-31 | $7700.00 | Window Closed / Lapsed |