Method of manufacturing self-aligned bit-line and device manufactured therby

Claim 1

An integrated circuit EPROM memory device comprising: a semiconductor substrate having devices therein to which electrical connections are to be made, a tunnel oxide layer on said substrate, an array of gate electrode stacks formed on said tunnel oxide layer, said stacks having sidewalls with trench spaces therebetween down to said tunnel oxide layer, said trench spaces comprising wider drain trench spaces and narrower source trench spaces, said stacks having sidewalls, said gate electrode stacks including a doped polysilicon floating gate electrode over said tunnel oxide layer, an interelectrode dielectric layer over said floating gate electrode, a doped polysilicon control gate electrode over said interelectrode dielectric layer, a silicon dioxide dielectric layer over said control gate electrode, and a silicon nitride (Si 3 N 4 ) layer over said silicon dioxide layer, ion implanted source/drain regions layer formed between said stacks with alternating source regions and drain regions below said trench spaces between said sidewalls, spacer dielectric structures adjacent to said sidewalls of said drain trench spaces, spacer dielectric plugs filling said source trench spaces, a blanket dielectric layer over said stacks and said spacer dielectric plugs, conductive metal bit-lines extending across said stacks and down into contact with said drain regions through said drain trench spaces, whereby said memory devices include a self-aligned bit-line structure formed simultaneously with electrical contacts to the drain electrodes.