Semiconductor device having field-shield isolation structures and a method of making the same

Claim 2

A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a plurality of spaced field-shield isolation structures formed on a surface of the semiconductor substrate and extending parallelly in a first direction so as to provide element-forming regions at spaces between every adjacent two of the field-shield isolation structures; a pair of impurity diffusion layers of a second conductivity type different from said first conductivity type formed in the surface of said semiconductor substrate at portions adjacent to opposite sides of each of said element-forming regions extending in said first direction; a plurality of spaced lateral regions defined on the surface of said semiconductor substrate to extend in a second direction intersecting with said first direction; and a plurality of gate electrode structures formed on the surface of said semiconductor substrate at portions corresponding to intersections of said lateral regions and said element-forming regions, respectively, and insulated from said semiconductor substrate, said gate electrode structures being aligned along said lateral regions; wherein semiconductor elements are formed at said intersections, respectively, each being formed of a pair of portions of said impurity diffusion layers disposed at one of the intersections, a channel region formed between said portions of the diffusion layers and one of said gate electrode structures formed at the one intersection.

Claim 3

A semiconductor device according to claim 1, wherein each of said field-shield isolation structures includes at least a shield electrode formed on the surface of said semiconductor substrate with an insulating film interposed therebetween and extending in said first direction.

Claim 4

A semiconductor device according to claim 1, further comprising a plurality of gate wiring layers formed on the lateral regions, respectively, each of said gate wiring layers operating as a control gate common to a group of the semiconductor elements disposed along an associated one of the lateral regions.

Claim 5

A semiconductor device according to claim 1, wherein the semiconductor elements constitute a semiconductor memory device having a plurality of memory cells formed of said semiconductor elements and said gate wiring layers operate as word lines of the semiconductor memory device.

Claim 6

A semiconductor device according to claim 1, wherein the semiconductor elements constitute a semiconductor memory device having a plurality of memory cells formed of said semiconductor elements and one of said pair of diffusion layers operates as a bit line of the semiconductor memory device.

Claim 7

A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a plurality of spaced field-shield isolation structures formed on a surface of the semiconductor substrate and extending parallelly in a longitudinal direction so as to provide element-forming regions at spaces between every adjacent two of the field-shield isolation structures; a pair of impurity diffusion layers of a second conductivity type different from said first conductivity type formed in the surface of said semiconductor substrate at portions adjacent to longitudinal opposite sides of each of said element-forming regions; a plurality of spaced lateral regions defined on the surface of said semiconductor substrate to extend in a lateral direction intersecting with said longitudinal direction; and a plurality of individual semiconductor elements formed on the surface of said semiconductor substrate at portions corresponding to intersections of said lateral regions and said element-forming regions, respectively, each semiconductor element including a pair of portions of said impurity diffusion layers disposed at one of the intersections and a channel region formed between said portions of the diffusion layers.

Claim 8

A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a plurality of spaced field-shield isolation structures formed on a surface of the semiconductor substrate and extending parallelly in a longitudinal direction so as to provide element-forming regions at spaces between every adjacent two of the field-shield isolation structures; a pair of impurity diffusion layers of a second conductivity type different from said first conductivity type formed in the surface of said semiconductor substrate at portions adjacent to longitudinal opposite sides of each of said element-forming regions; a plurality of spaced lateral regions defined on the surface of said semiconductor substrate to extend in a lateral direction intersecting with said longitudinal direction; and a plurality of individual semiconductor elements formed on the surface of said semiconductor substrate at portions corresponding to intersections of said lateral regions and said element-forming regions, respectively, each semiconductor element including a pair of portions of said impurity diffusion layers disposed at one of the intersections and a channel region formed between said portions of the diffusion layers.

Claim 9

A semiconductor device according to claim 6, wherein each of said field-shield isolation structures includes a shield electrode formed on the surface of said semiconductor substrate and extending in the longitudinal direction and sidewall insulating films formed to cover opposite longitudinal side walls of the shield electrode.

Claim 10

A semiconductor device according to claim 6, wherein each of said semiconductor elements includes a gate electrode structure formed on the surface of the semiconductor substrate at one of the intersections.

Claim 11

A semiconductor device according to claim 8, wherein said gate electrode structure includes a gate insulating film formed on the surface of said semiconductor substrate at said one intersection, a floating gate formed on said gate insulating film and a control gate formed on said floating gate with an interlayer insulating film therebetween.

Claim 12

A semiconductor device according to claim 9, further comprising a gate wiring layer formed over the gate electrode structures of a group of the semiconductor elements aligned along one of the lateral regions, said gate wiring layer operating as the control gate common to said group of the semiconductor elements.

Claim 13

A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a plurality of spaced field-shield isolation structures formed on a surface of the semiconductor substrate and extending parallelly in a first direction so as to provide element-forming regions at spaces between every adjacent two of the field-shield isolation structures; a pair of impurity diffusion layers of a second conductivity type different from said first conductivity type formed in the surface of said semiconductor substrate at portions adjacent to opposite sides of each of said element-forming regions extending in said first direction; a plurality of spaced lateral regions defined on the surface of said semiconductor substrate to extend in a second direction perpendicular to said first direction; a plurality of discrete gate electrodes formed on the surface of said semiconductor substrate at portions corresponding to intersections of said lateral regions and said element-forming regions, respectively, in electrically insulated relationship with said semiconductor substrate, said gate electrodes being aligned along said lateral regions; and a plurality of gate wiring layers formed on said lateral regions, respectively, each of said gate wiring layers being disposed over a group of the gate electrodes aligned with one of the lateral regions in electrically insulated relationship with the gate electrodes; wherein semiconductor elements are formed at said intersections, respectively, each being formed of a pair of portions of said impurity diffusion layers disposed at one of the intersections, a channel region formed between said portions of the diffusion layers and one of said gate electrodes formed at the one intersection and operating as a floating gate thereof and each of said gate wiring layers operating as a control gate common to the group of the semiconductor elements on which the gate wiring layer is disposed.

Claim 14

A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a plurality of spaced field-shield isolation structures formed on a surface of the semiconductor substrate and extending parallelly in a first direction so as to provide element-forming regions at spaces between every adjacent two of the field-shield isolation structures; a pair of impurity diffusion layers of a second conductivity type different from said first conductivity type formed in the surface of said semiconductor substrate at portions adjacent to opposite sides of each of said element-forming regions extending in said first direction; a plurality of spaced lateral regions defined on the surface of said semiconductor substrate to extend in a second direction perpendicular to said first direction; a plurality of discrete gate electrodes formed on the surface of said semiconductor substrate at portions corresponding to intersections of said lateral regions and said element-forming regions, respectively, in electrically insulated relationship with said semiconductor substrate, said gate electrodes being aligned along said lateral regions; and a plurality of gate wiring layers formed on said lateral regions, respectively, each of said gate wiring layers being disposed over a group of the gate electrodes aligned with one of the lateral regions in electrically insulated relationship with the gate electrodes; wherein semiconductor elements are formed at said intersections, respectively, each being formed of a pair of portions of said impurity diffusion layers disposed at one of the intersections, a channel region formed between said portions of the diffusion layers and one of said gate electrodes formed at the one intersection and operating as a floating gate thereof and each of said gate wiring layers operating as a control gate common to the group of the semiconductor elements on which the gate wiring layer is disposed.

Claim 15

A semiconductor device having a field-shield isolation structure comprising: a first insulating film formed on a semiconductor substrate; a shield electrode formed on said first insulating film, said shield electrode constituting said field-shield isolation structure together with said first insulating film; a first gate electrode of a transistor formed on said semiconductor substrate at a portion adjacent to said shield electrode with a second insulating film interposed therebetween and insulated from said semiconductor with a third insulating film; an impurity diffusion layer formed in said semiconductor substrate at a portion under said second insulating film and acting as a source or drain of said transistor; and wherein said gate electrode operates as a floating gate of said transistor.

Claim 16

A semiconductor device having a field-shield isolation structure comprising: a first insulating film formed on a semiconductor substrate; a shield electrode formed on said first insulating film, said shield electrode constituting said field-shield isolation structure together with said first insulating film; a first gate electrode of a transistor formed on said semiconductor substrate at a portion adjacent to said shield electrode with a second insulating film interposed therebetween and insulated from said semiconductor with a third insulating film; an impurity diffusion layer formed in said semiconductor substrate at a portion under said second insulating film and acting as a source or drain of said transistor; and wherein said gate electrode operates as a floating gate of said transistor.

Claim 17

A semiconductor device according to claim 12, wherein said first insulating film has a thickness larger than that of said third insulating film.

Claim 18

A semiconductor device according to claim 12, further comprising a second gate electrode formed on said first gate electrode with a fourth insulating film interposed therebetween.

Claim 19

A semiconductor device comprising: a first insulating film formed on a semiconductor substrate; first and second electrodes formed on said first insulating film for element-isolation; impurity diffusion layers formed in said semiconductor substrate at portions adjacent to respective end portions of said first and second electrodes and opposite to each other; an active region formed between said impurity diffusion layers in said semiconductor substrate; and a gate electrode structure of a transistor formed on said active region with a second insulating film interposed therebetween; and wherein said gate electrode structure includes a floating gate wholly surrounded by an insulating layer.

Claim 20

A semiconductor device comprising: a first insulating film formed on a semiconductor substrate; first and second electrodes formed on said first insulating film for element-isolation; impurity diffusion layers formed in said semiconductor substrate at portions adjacent to respective end portions of said first and second electrodes and opposite to each other; an active region formed between said impurity diffusion layers in said semiconductor substrate; and a gate electrode structure of a transistor formed on said active region with a second insulating film interposed therebetween; and wherein said gate electrode structure includes a floating gate wholly surrounded by an insulating layer.

Claim 21

A semiconductor device according to claim 15, wherein said gate electrode structure further includes a control gate formed on said floating gate with a third insulating film interposed therebetween.

Claim 22

A semiconductor device according to claim 15, wherein said insulating layer includes a sidewall insulating layer for insulating between each of said first and second electrodes and said gate electrode structure and surrounding sides of each of said first and second electrodes.

Claim 23

A semiconductor device according to claim 17, wherein said sidewall insulating layer is formed on said impurity diffusion layers.