Quasi-double balanced dual-transformer dual FET mixer, which achieves better isolation by using a first and second diplexer, and a transmission line RF balun

Claim 1

A mixer comprising: a first and a second FET transistor each having a gate and a drain and a source, the first and second FET transistors having their gates tied to one another and said sources connected together such that the first and second FET transistors are in series; a local oscillator (LO) input circuit having an unbalanced input port for connecting to an external local oscillator signal source, and an output port for connection to said gates and sources of the first and second FET transistors such that the first and second FET transistors are driven on and off in response to said externally applied LO signal; a first diplexer circuit having a primary port coupled between said first FET transistor drain and source terminals and a secondary port having first and second secondary port terminals, said first diplexer comprising the combination of a first inductor serially connected to a first capacitor in parallel with said primary port and a second capacitor serially connected between said first diplexer primary port and said first diplexer secondary port; a second diplexer circuit having a primary port coupled between said second FET transistor drain and source terminals and secondary port having third and fourth secondary port terminals, said second diplexer comprising the combination of a second inductor serially connected to a third capacitor in parallel with said primary port and a fourth capacitor serially connected between said second diplexer primary port and said second diplexer secondary port; an RF and IF coupling network comprising a flux-coupled IF transformer and a transmission line RF balun; said flux-coupled IF transformer having two pairs of flux-coupleable windings and a center tap between said two pairs of windings, and further having a first port connected to said second and third terminals of said secondary ports of said first and second diplexer circuits respectively, and a second port connected to a two-terminal IF port; said transmission line RF balun having first and second terminals of a primary port and second and third terminals of a secondary port, said first terminal serially connected to said first capacitor, said second terminal connected to said second capacitor, said third terminal connected to a first RF port terminal, and said fourth terminal connected to a second RF port terminal; and a bias circuit coupleable to an external bias source for providing a direct current (dc) bias to the drains of said first and second FET transistors coupled to said center tap and comprising first and second resistors each connected in parallel with said first and second resistors; whereby a dc circuit path is defined between said bias source, said two transformer windings, said first and second resistors, and said FET transistor drain terminals, and said FET transistor source terminals.