Abstract A DRAM controller (18) for controlling access to a system memory (11) is provided. Prioritizer circuit (38) causes a first plurality of buffers (42) to pass an address signal (46) for a first requesting circuit to a primary address bus (48) and a second plurality of buffers (44) to pass an address signal (46) for a next requesting circuit to a secondary address bus (50). The pages requested on primary address bus (48) and secondary address bus (50) are compared with the active page of each memory bank (11) stored in registers (52), (54), (56), and (58) by first and second plurality of comparators (60) and (70) to determine if the pages are active. The output of each of the first and second plurality of comparators (60) and (70) is coupled to a corresponding bank controller in a plurality of bank controllers (84) to produce control signals on control lines (26). A first bank decoder (80) enables an appropriate one of the plurality of bank controllers (84) to precharge an appropriate control line (26) corresponding to input from first plurality of comparators (60). The first requesting circuit signals DRAM controller (18) through a multiplexer (94) that the first requesting circuit is ready to finish accessing system memory (11) thereby allowing second bank decoder (82) to enable an appropriate one of the plurality of bank controllers (84) to precharge an appropriate control line (26) corresponding to input from second plurality of comparators (70).
Inventors
👤 Van Minh Nguyen
👤 Patrick W. Bosshart
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-11-04 06:43
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0215
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
181 words
A memory controller for a memory including a plurality of memory banks, comprising: an input for receiving memory access requests; a primary address bus for memory bank and page addresses of a primary memory access request; a secondary address bus for memory bank and page addresses of a secondary memory access request; a first memory bank controller with inputs coupled to said primary address bus and said secondary address bus and with outputs coupled to a first memory bank; a second memory bank controller with inputs coupled to said primary address bus and said secondary address bus and with outputs coupled to a second memory bank; a prioritizer for prioritizing memory access requests and selecting addresses for said primary and secondary address busses; and wherein when an address on said secondary address bus is for a first page in said first memory bank and an address on said primary address bus is for a second page in said second memory bank, said first memory bank controller insures said first page is active prior to completion of said primary memory access request.
Claim 2
Dependent Claim
181 words
A memory controller for a memory including a plurality of memory banks, comprising: an input for receiving memory access requests; a primary address bus for memory bank and page addresses of a primary memory access request; a secondary address bus for memory bank and page addresses of a secondary memory access request; a first memory bank controller with inputs coupled to said primary address bus and said secondary address bus and with outputs coupled to a first memory bank; a second memory bank controller with inputs coupled to said primary address bus and said secondary address bus and with outputs coupled to a second memory bank; a prioritizer for prioritizing memory access requests and selecting addresses for said primary and secondary address busses; and wherein when an address on said secondary address bus is for a first page in said first memory bank and an address on said primary address bus is for a second page in said second memory bank, said first memory bank controller insures said first page is active prior to completion of said primary memory access request.
Claim 3
Dependent Claim
35 words
The controller of claim 1, wherein: registers maintain active page information for each of said memory banks; and comparators compare active page information of said registers to the page address on said secondary address bus.
Claim 4
Dependent Claim
19 words
The controller of claim 1, wherein: said memory bank controllers provide RAS and CAS signals to corresponding memory banks.