US5731970A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power conversion device and semiconductor module suitable for use in the device
Assignee: Hitachi Ltd
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Filing: 1995-06-07
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Granted: 1998-03-24
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Expires: 2015-06-07
Abstract
Abstract An inverter device includes plural modules, each module being formed by a series circuit having a parallel circuit of a first switching device and a first diode, and a parallel circuit of a second switching device and a second diode, allowing a reduced size, high reliability, high frequency switching and low noise. Each module forms one arm portion of the inverter. Lifetimes of the diodes and the switching devices are set in a manner to equalize losses in the inverter. Preferably, insulated gate bipolar transistors (IGBTs) formed by diffusion are used as the switching devices since the lifetimes of these devices can easily be adjusted to optimize design of the inverter.
Inventors
- 👤 Mutsuhiro Mori
- 👤 Ryuichi Saito
- 👤 Shin Kimura
- 👤 Syuuji Saitoo
- 👤 Kiyoshi Nakata
- 👤 Akira Horie
- 👤 Yoshihiko Koike
- 👤 Shigeki Sekine
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 15:26
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/483; H02M7/487; H02M7/003; H03; H03K; H03K17/00; H03K17/08; H03K17/081; H03K17/0814; H03K17/08148; H10; H10W; H10W76/00; H10W76/10; H10W76/12; H10W76/40; H10W76/42; H10W76/47; H10W90/00; H10W72/00; H10W72/50; H10W72/541; H10W72/547; H10W72/5473; H10W72/5475; H10W72/551; H10W72/552; H10W72/5524; H10W72/851; H10W72/874; H10W72/884; H10W90/701; H10W90/751; H10W90/754; Y; Y10; Y10S; Y10S257/00; Y10S257/925
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
115 words
An inverter device comprising: a pair of d.c. terminals; a node at a potential intermediate between the potentials of said pair of d.c. terminals; a.c. terminals as many as the number of phases; a plurality of arms each connected between the d.c. terminal and the a.c. terminal, comprising two parallel circuits in series, each parallel circuit including a switching device and a diode opposite in polarity to said switching device; and a plurality of diodes each connected between a node of the two parallel circuits of the arm and, said node at a potential intermediate between the potentials of said pair of d.c. terminals, wherein each of said arms is formed by a single module.
Claim 2
Dependent Claim
115 words
An inverter device comprising: a pair of d.c. terminals; a node at a potential intermediate between the potentials of said pair of d.c. terminals; a.c. terminals as many as the number of phases; a plurality of arms each connected between the d.c. terminal and the a.c. terminal, comprising two parallel circuits in series, each parallel circuit including a switching device and a diode opposite in polarity to said switching device; and a plurality of diodes each connected between a node of the two parallel circuits of the arm and, said node at a potential intermediate between the potentials of said pair of d.c. terminals, wherein each of said arms is formed by a single module.
Claim 3
Dependent Claim
137 words
An inverter device used to drive a vehicle on a trolley voltage of at least 1500 volt, comprising: a pair of d.c. terminals; a node at an intermediate potential between the potentials of said pair of d.c. terminals; a.c. terminals as many as the number of phases; a plurality of arms each connected between the d.c. terminal and the a.c. terminal, comprising two parallel circuit in series, each parallel circuit including an insulated gate bipolar transistor and a diode opposite in conducting direction to said insulated gate bipolar transistor, each of the parallel circuits connected between the d.c. terminal and the a.c. terminal; and a plurality of diodes each connected between a node of said two parallel circuits of the arm and, said node at a potential intermediate between the potentials of said pair of d.c. terminals.
Claim 4
Dependent Claim
137 words
An inverter device used to drive a vehicle on a trolley voltage of at least 1500 volt, comprising: a pair of d.c. terminals; a node at an intermediate potential between the potentials of said pair of d.c. terminals; a.c. terminals as many as the number of phases; a plurality of arms each connected between the d.c. terminal and the a.c. terminal, comprising two parallel circuit in series, each parallel circuit including an insulated gate bipolar transistor and a diode opposite in conducting direction to said insulated gate bipolar transistor, each of the parallel circuits connected between the d.c. terminal and the a.c. terminal; and a plurality of diodes each connected between a node of said two parallel circuits of the arm and, said node at a potential intermediate between the potentials of said pair of d.c. terminals.
Claim 5
Dependent Claim
151 words
An inverter device comprising: a pair of d.c. terminals; a node at a potential intermediate between the potentials of said pair of d.c. terminals; a.c. terminals as many as the number of phases; a plurality of arms each connected between the d.c. terminal and the a.c. terminal, comprising two parallel circuits in series, each parallel circuit including a switching device and a diode opposite in polarity to said switching device; and a plurality of diodes each connected between a node of the two parallel circuits of the arm and, said node at a potential intermediate between the potentials of said pair of d.c. terminals, wherein a lifetime of the switching device close to the d.c. terminal and at least one of the devices forming the parallel circuit having the diode opposite in polarity to the device is different from that of device forming the parallel circuit close to the a.c. terminal.
Claim 6
Dependent Claim
151 words
An inverter device comprising: a pair of d.c. terminals; a node at a potential intermediate between the potentials of said pair of d.c. terminals; a.c. terminals as many as the number of phases; a plurality of arms each connected between the d.c. terminal and the a.c. terminal, comprising two parallel circuits in series, each parallel circuit including a switching device and a diode opposite in polarity to said switching device; and a plurality of diodes each connected between a node of the two parallel circuits of the arm and, said node at a potential intermediate between the potentials of said pair of d.c. terminals, wherein a lifetime of the switching device close to the d.c. terminal and at least one of the devices forming the parallel circuit having the diode opposite in polarity to the device is different from that of device forming the parallel circuit close to the a.c. terminal.
Claim 7
Dependent Claim
135 words
An inverter device comprising: a pair of d.c. terminals; a node at a potential intermediate between the potentials of said pair of d.c. terminals; a.c. terminals as many as the number of phases; a plurality of arms each connected between the d.c. terminal and the a.c. terminal, comprising two parallel circuits in series, each parallel circuit including an insulated gate bipolar transistor and a diode opposite in polarity to said insulated gate bipolar transistor; and a plurality of diodes each connected between a node of the two parallel circuits of the arm and, said node at a potential intermediate between the potentials of said pair of d.c. terminals, wherein one of the insulated gate bipolar transistors and diode of the parallel circuit of each arm is formed on a semiconductor substrate produced by Czochralski method.
Claim 8
Dependent Claim
135 words
An inverter device comprising: a pair of d.c. terminals; a node at a potential intermediate between the potentials of said pair of d.c. terminals; a.c. terminals as many as the number of phases; a plurality of arms each connected between the d.c. terminal and the a.c. terminal, comprising two parallel circuits in series, each parallel circuit including an insulated gate bipolar transistor and a diode opposite in polarity to said insulated gate bipolar transistor; and a plurality of diodes each connected between a node of the two parallel circuits of the arm and, said node at a potential intermediate between the potentials of said pair of d.c. terminals, wherein one of the insulated gate bipolar transistors and diode of the parallel circuit of each arm is formed on a semiconductor substrate produced by Czochralski method.
Claim 9
Dependent Claim
183 words
An inverter device comprising: a pair of d.c. terminals; a.c. terminals equal to the number of phases of the inverter device; and a plurality of arms each connected between one of the d.c. terminals and one of the a.c. terminals, each arm comprising at least one parallel circuit, each parallel circuit including an insulated gate bipolar transistor and a diode opposite in conducting direction to said insulated gate bipolar transistor, each of the parallel circuits connected between the d.c. terminal and the a.c. terminal to which the corresponding arm is connected; wherein in at least one of said parallel circuits said diode has a recovery current of which a peak-to-peak value is at most 0.55 times a rated current of the insulated gate bipolar transistor of said at least one parallel circuit, and a recovery time in which the recovery current is attenuated from the peak-to-peak value to one tenth thereof is at least 0.75 times a resonance period obtained from a wiring inductance and a parasitic capacitance of said insulated bipolar transistor and said diode of said at least one parallel circuit.
Claim 10
Dependent Claim
183 words
An inverter device comprising: a pair of d.c. terminals; a.c. terminals equal to the number of phases of the inverter device; and a plurality of arms each connected between one of the d.c. terminals and one of the a.c. terminals, each arm comprising at least one parallel circuit, each parallel circuit including an insulated gate bipolar transistor and a diode opposite in conducting direction to said insulated gate bipolar transistor, each of the parallel circuits connected between the d.c. terminal and the a.c. terminal to which the corresponding arm is connected; wherein in at least one of said parallel circuits said diode has a recovery current of which a peak-to-peak value is at most 0.55 times a rated current of the insulated gate bipolar transistor of said at least one parallel circuit, and a recovery time in which the recovery current is attenuated from the peak-to-peak value to one tenth thereof is at least 0.75 times a resonance period obtained from a wiring inductance and a parasitic capacitance of said insulated bipolar transistor and said diode of said at least one parallel circuit.
Claim 11
Dependent Claim
15 words
An inverter device according to claim 5, wherein said parallel circuits are set in modules.
Claim 12
Dependent Claim
22 words
An inverter device according to claim 5, wherein said diodes of said parallel circuits each have a pn-junction and a Schottky barrier.
Claim 13
Dependent Claim
236 words
An inverter device comprising: a pair of d.c. terminals; a.c. terminals equal to the number of phases of the inverter device; and a plurality of arms each connected between one of the d.c. terminals and one of the a.c. terminals, each arm comprising at least one parallel circuit, each parallel circuit including an insulated gate bipolar transistor and a diode opposite in conducting direction to said insulated gate bipolar transistor, each of the parallel circuits connected between the d.c. terminal and the a.c. terminal to which the corresponding arm is connected; wherein in at least one of said parallel circuits said diode includes a first semiconductor region of one conductivity type having one main surface, a second semiconductor region of a second conductivity type extending from a plurality of selected portions of said main surface into the inside of said first semiconductor region, a third semiconductor region of the second conductivity type extending from said main surface into the inside of said first semiconductor region and across adjacent portions of said second semiconductor region, said third semiconductor region having a depth smaller than that of said second semiconductor region, a first electrode formed on said main surface so as to form an ohmic junction with said second semiconductor region and form a Schottky junction with said third semiconductor region, and a second electrode provided so as to form an ohmic junction with said first semiconductor region.
Claim 14
Dependent Claim
236 words
An inverter device comprising: a pair of d.c. terminals; a.c. terminals equal to the number of phases of the inverter device; and a plurality of arms each connected between one of the d.c. terminals and one of the a.c. terminals, each arm comprising at least one parallel circuit, each parallel circuit including an insulated gate bipolar transistor and a diode opposite in conducting direction to said insulated gate bipolar transistor, each of the parallel circuits connected between the d.c. terminal and the a.c. terminal to which the corresponding arm is connected; wherein in at least one of said parallel circuits said diode includes a first semiconductor region of one conductivity type having one main surface, a second semiconductor region of a second conductivity type extending from a plurality of selected portions of said main surface into the inside of said first semiconductor region, a third semiconductor region of the second conductivity type extending from said main surface into the inside of said first semiconductor region and across adjacent portions of said second semiconductor region, said third semiconductor region having a depth smaller than that of said second semiconductor region, a first electrode formed on said main surface so as to form an ohmic junction with said second semiconductor region and form a Schottky junction with said third semiconductor region, and a second electrode provided so as to form an ohmic junction with said first semiconductor region.
Claim 15
Dependent Claim
15 words
An inverter device according to claim 8, wherein said parallel circuits are set in modules.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-23 | 2001-09-22 | 2002-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-23 | 2005-09-22 | 2006-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-23 | 2009-09-22 | 2010-03-24 | $7700.00 | Window Closed / Lapsed |